參數(shù)資料
型號： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁數(shù)： 52/70頁
文件大小： 1395K
代理商： MB86860
Specifications subject to changes without prior notice
63
MB86860 SPARClite
9.
APPENDIX A [ SPARClite Instruction Sets and CPI ]
SPARClite
[4]
Name
Operation
MB8686X
[1]
MB8683X
Load and Store Instructions
LDSB
(LDSBA)
Load Signed Byte
(from Alternate Space)
1
[2]
1
LDSH
(LDSHA)
Load Signed Halfword
(from Alternate Space)
1
[2]
1
LDUB
(LDUBA)
Load Unsigned Byte
(from Alternate Space)
1
[2]
1
LDUH
(LDUHA)
Load Unsigned Halfword
(from Alternate Space)
1
[2]
1
LD
(LDA)
Load word
(from Alternate Space)
1
[2]
1
LDD
(LDDA)
Load Doubleword
(from Alternate Space)
1
[2]
2
LDF
Load Floating Point
not supported
LDFF
Load Double Floating Point
not supported
LDFSR
Load Floating-Point State Register
not supported
LDC
Load Coprocessor
not supported
LDDC
Load Double Coprocessor
not supported
LDCSR
Load Coprocessor State Register
not supported
STB
(STBA)
Store Byte
(into Alternate Space)
1 or 2
[6]
1
STH
(STHA)
Store Harfword
(into Alternate Space)
1 or 2
[6]
1
ST
(STA)
Store Word
(into Alternate Space)
1 or 2
[6]
1
STD
(STDA)
Store Doubleword
(into Alternate Space)
1 or 2
[6]
2
STF
Store Floating-Point
not supported
STDF
Store Double Floating-Point
not supported
STFSR
Store Floating-Point State Register
not supported
STDFQ
Store Double Floating-Point Queue
not supported
STC
Store Coprocessor
not supported
STDC
Store Double Coprocessor
not supported
STCSR
Store Coprocessor State Register
not supported
STDCQ
Store Double Coprocessor Queue
not supported
LDSTUB
(LDSTUBA)
Atomic Load-Store Unsigned Byte
(in Alternate Space)
3
SWAP
(SWAPA)
Swap r-register with Memory
(in Alternate Space)
3
Arithmetic/Logical/Shift
ADD
(ADDcc)
Add
(and modify icc)
1
ADDX
(ADDXcc)
Add with Carry
(and modify icc)
1
SUB
(SUBcc)
Subtract
(and modify icc)
1
SUBX
(SUBXcc)
Subtract with Carry
(and modify icc)
1
TADDcc
(TADDccTV) Tagged Add and Modify icc
(and Trap on overflow)
1
TSUBcc
(TSUBccTV) Tagged Subtract and Modify icc
(and Trap on overflow)
1
DIVSCC
Divide Step
not supported
1
SCAN
Scan for MSB
not supported
1
SDIV
(SDIVcc)
Integer Divide
(and modify icc)
37
not supported
SMUL
(SMULcc)
Integer Multiply
(and modify icc)
6
max5
[5]
MULScc
Multiply Step and Modify icc
1
UDIV
(UDIVcc)
Unsigned Divide (integer)
37
not supported
UMUL
(UMULcc)
Unsigned Multiply (integer)
6
max5
[5]
AND
(ANDcc)
And
(and modify icc)
1
ANDN
(ANDNcc)
And Not
(and modify icc)
1
OR
(Orcc)
Inclusive Or
(and modify icc)
1
ORN
(ORNcc)
Inclusive Or Not
(and modify icc)
1
XOR
(XORcc)
Exclusive Or
(and modify icc)
1
XNOR
(XNORcc)
Exclusive Nor
(and modify icc)
1
SLL
Shift Left Logical
1
SRL
Shift Right Logical
1
SRA
Shift Right Arithmetic
1
SETHI
Set High 22 Bit of r-register
1
SAVE
Save Caller's Window
1
RESTORE
Restore Caller's Window
1
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