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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 53/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
64
MB86860 SPARClite
Control
Transfer
Bicc
Branch on Integer Condition Codes
1
[3]
1
[3]
Fbicc
Branch on Floating-Point Condition Codes
not supported
CBccc
Branch on Coprocessor Condition Codes
not supported
CALL
Call
1
[3]
1
[3]
JMPL
Jump and Link
1
[3]
2
[3]
RETT
Return from Trap
1
[3]
2
[3]
Ticc
Trap on Integer Condition Codes
1
3
Read/Write Control Registers
RDASR
Read Ancillary Register
1
RDY
Read Y Register
1
RDPSR
Read Processor State Register
1
RDWIM
Read Window Invalid Mask
1
RDTBR
Read Trap Base Register
1
WRASR
Write Ancillary State Register
1
WRY
Write Y Register
1
WRPSR
Write Processor State Register
1
WRWIM
Write Window Invalid Mask
1
WRTBR
Write Trap Base Register
1
UNIMP
Unimplemented Instruction
1
3
FLUSH
Instruction Cache Flash
4
not supported
FP(CP) Operations
Fpop
Floating-Point Unit Operations
not supported
Cpop
Coprocessor Operations
not supported
Notes:
1. MB8686X CPI assume Worst Case in 1 command execution.
2. For ASI=0xc, 0xd, 0x10-0x18, 0x31access, the CPI changes.
3. Assumes that delay slots are buried in usable instructions
4. Assumes that all CPI hit to I-cache and d-cache
5. 32bit x 0bit
1cycle
32bit x 8bit
2cycle
32bit x 16bit
3cycle
32bit x 32bit
5cycle
6. Execution of stores in IMB odd clock cycles takes 2 clocks and in even cycles 1 clock.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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