參數(shù)資料
型號(hào)： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 58/70頁(yè)
文件大?。?/td> 1395K
代理商： MB86860
Specifications subject to changes without prior notice
69
MB86860 SPARClite
SPARClite Signals (3/3)
Pin Names
Pin Status
Explanation
Sleep
Mode
Bus
Grant
LOCK#
(output)
O(Z)
Bus Lock Signal. This is a control signal asserted by the processor to indicate
to the system that the current bus transaction requires more than one transfer on
the bus. The Atomic Load Store instruction for example requires contiguous bus
transactions which cause the LOCK# is active. LOCK# is asserted with the
assertion of AS# and remains active until READY# is asserted at the end of the
locked transaction.
BMODE16#
BMODE32#
(input)
--------
Boot Mode Bus Width. These signals are sampled at negation of RESET#.
And the processor determine the bus width for CS0# area based on the
combination of those signals. (BMODE16#,BMODE32#)=(0,0) means that bus
width are 8bit, (01),(10), (11) means 16bit, 32bit, 64bit respectively.
ERROR#
(input)
O(V)
Error Signal. Asserted by the CPU to indicate that it has halted in an error state
as a result of encountering a synchronous trap while traps are disabled. In this
situation the CPU saves the PC and nPC registers, sets the tt value in the TBR,
enters into an error state and asserts the ERROR# signal. The system can monitor
the ERROR# pin and initiate a reset under the error condition. This pin is high on
reset.
IRL<3:0>
(input)
--------
Interrupt Request Level. The value on these pins defines the external
interrupt level. IRL<3:0>=1111 forces a non-maskable interrupt. IRL value of 0000
indicates no pending interrupts. All other values indicate maskable interrupts as
enabled in the PIL field of the processor status register (PSR). Interrupts should
be latched and prioritized by external logic and should be held pending until
acknowledged by the processor.
SDRAM Signals
Pin Names
Pin Status
Explanation
SleepMode
SCLK
(output)
O(L)
SDRAM clock. Should be linked to SDRAM clock input. Clock frequency is the
same as internal IMB bus frequency.
CKE
(ouput)
O(H)
SDRAM Clock Enable signal.
SRAS#
(output)
O(H)
SDRAM RAS signal.
SCAS#
(output)
O(H)
SDRAM CAS signal.
SWE#
(output)
O(H)
SDRAM Write Enable signal.
SCS3#
-
SCS0#
(output)
O(H)
SDRAM Chip Select signals.
SBA<1:0>
(output)
O(X)
SDRAM Bank Select signal.
SADR<12:0
>
O(X)
SDRAM Address signal. Addresses are multiplexed.
相關(guān)PDF資料
PDF描述
MB86931-20ZF-G 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256
MB86931-40ZF-G 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256
MB86933H-20PF-G 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160
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