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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 19/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
30
MB86860 SPARClite
Table 5-2 Access Order between RB and WB (continued)
Access Type
hit judgment
Operation
Burst
Access
Non-cache
Store
IB: hit
First writes the WB, then writes data to external memory.
OFF
area
ASI==8, 9
IB: miss
(data access)
Store
RB: hit
First writes the WB, then writes data to external memory.
OFF
ASI==a, b
Invalidates tags if there is a hit to the RB.
&
RB: miss
NC==1
Store
DON’T
First writes the WB, then writes data to external memory.
OFF
ASI !=
CARE
8,9,a, b
Load
RB: hit
First writes the WB to external memory, then reads data
from
OFF
ASI==a, b
external memory or I/O and sends it to the CPU Core.
Basical-
&
RB: miss
ly, RB tags are not updated but are invalidated if there is a
hit
NC==1
to the RB. Data size is decided at IMSIZE<1: 0>.
Load
RB: hit
First writes the WB to external memory, then reads data
from
OFF
ASI !=
RB: miss
external memory or I/O and sends it to the CPU Core. Data
is
8,9,a, b
not written to the RB. Data size is decided at IMSIZE<1:
0>.
Non-cache
Load/Fetch
IB: miss
First writes the WB to external memory, then reads data
from
OFF
area
ASI==8, 9
external memory or I/O and sends it to the CPU Core.
(instruction)
&
IB: hit
Data size is decided at IMSIZE<1: 0>.
NC==1
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