參數(shù)資料
型號(hào)： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 49/70頁(yè)
文件大小： 1395K
代理商： MB86860
Specifications subject to changes without prior notice
60
MB86860 SPARClite
7.
Bi-endian Function
The SS200 uses the load/store instruction to select access data byte address endian- Big endian or Little endian. Endian
is specified by the DE (Default Endian) bit of the SS200 Core PSR Register. “0” indicates big endian and “1” indicates
little endian. After a reset, big endian (DE : 0) is effective. Bi-endian specification is valid only for data access. Please
note that instruction fetches are fixed to big endian and have no relation to DE bit settings. In the SS200, internal
registers mapped in memory spaces should be accessed as word data.
During word access, register address bit
positions in these specifications are guaranteed without regard to DE bit settings.
When changes are made to little endian after a reset, the DE bit must be set before executing load/store instructions.
Also, for DE bit changes, set data caches while off, or flush data cache contents after setting. The following indicates
the correspondences between data and addresses specified by load/store instructions of each access type.
bit63
←
64bit bus
→bit0
Addresses in case of Big Endian
=>
0
1
2
3
4
5
6
7
00
a
b
c
d
e
f
g
h
Addresses in case of Little
Endian
=>
7
6
5
4
3
2
1
0
Figure 7-1
1.
Byte Access ( ldub,ldsb,stb)
Table 7-1
Instruction
Address
little
BIG
ldb
0
h
a
1
g
b
2
f
c
3
e
d
4
d
e
5
c
f
6
b
g
7
a
h
2.
Half word Access ( iduh,ldsh,sth)
Table 7-2
Instruction
Address
little
BIG
ldh
0
gh
ab
2
ef
cd
4
cd
ef
6
ab
gh
3.
Word Access ( ld, st)
Table 7-3
Instruction
Address
little
BIG
ld
0
efgh
abcd
4
abcd
efgh
4.
Double word Access ( ldd, std)
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