參數(shù)資料
型號(hào)： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 22/70頁(yè)
文件大?。?/td> 1395K
代理商： MB86860
Specifications subject to changes without prior notice
33
MB86860 SPARClite
5.3.3. Signals
SDRAM bus signals are explained below. Signal direction takes the BIU Unit as the standard.
Table 5-4
SCLK
(output)
SDRAM clock signal. Should be linked to SDRAM clock input. Clock frequency is
the same as internal IMB bus frequency.
CKE
(ouput)
SDRAM Clock Enable signal.
SRAS#
(output)
SDRAM RAS signal.
SCAS#
(output)
SDRAM CAS signal.
SWE#
(output)
SDRAM Write Enable signal.
SCS3# -
SCS0#
(output)
SDRAM Chip Select signals.
SBA[1:0]
(output)
SDRAM Bank Select signal.
SADR[12:0]
(output)
SDRAM Address signal. Addresses are multiplexed.
SDQ[63:0]
(I/O)
SDRAM Data Bus.
SDQM[0:7]
(output)
SDRAM Input Mask (Output Enable signal).
SDP[0:7]
(I/O)
SDRAM Parity signal.
5.3.4. Parity Generation
Check Functions
Parity checks during SDRAM reads and Parity Generation during SDRAM writes are performed by setting 1 to bit1(SPE)
of the SDRAM Configuration Register (SDCFG). The SDRAM I/F Unit performs each odd/even parity generation and
check in the SDQ signal byte in accordance with the setting of SDCFG bit2(SPC).
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