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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 25/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
35
MB86860 SPARClite
5.3.5.4. Examples of SDRAM Connections
Here we discuss connections between SDRAM buses and SDRAM. Please note that there are restrictions on addresses
assigned to SDRAM areas because of connection configurations. Examples of this are shown below.
A 64Mbit 16bit-width SDRAM is used, and in the following connection configuration using 1 SCS# signal (SCS0#) 32M
bytes of SDRAM space is configured.
Addresses which can be assigned to the SDRAM spaces in this example are in the ranges shown below.
Start Address
End Address
Capacity
Area 1
0x0000 0000
0x01FF FFFF
32Mbyte
Area 2
0x0800 0000
0x09FF FFFF
32Mbyte
Area 3
0x1000 0000
0X11FF FFFF
32Mbyte
:
Area n
(32Mbyte X 4) X (n-1)
Start address + 32Mbyte
32Mbyte
All areas are physically assigned to the same SDRAM spaces. Start addresses of the respective areas when used up to
all SCS# signals (SCS0#~3#) are multiples of the configured SDRAM spaces. Thus, if in the above example there is a
connction configuration which uses 4 SCS# signals (SCS0#~3#), SDRAM area start address is a multiple of 128M bytes
because there is a 128M byte (32M byte X 4) SDRAM space configuration. Moreover, end addresses depend on the
actual capacity of connected SDRAM, and in the above example they become addresses which add actual SDRAM
capacity of 32M bytes to the start address.
The following material shows examples of possible SDRAM connection configurations in the light of the I/O drive
capacity restrictions of the SDRAM I/F. In these respective configurations SDRAM area address ranges are shown in
accordance with the SDRAM type used, but only Area 1 is described. Please note that address ranges up to areas 2~n
which show physically identical spaces also exist.
X16bit
SS200
DQM0,1
DATA[63:48]
SAD[12:0], RAS, CAS, WE, SBA[1:0], CKE, SCS0
SCLK
DQM2,3
DATA[47:32]
DQM4,5
DATA[31:16]
DQM6,7
DATA[15:00]
SDRAM
I/O Cell
Example
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