參數(shù)資料
型號(hào)： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 18/70頁(yè)
文件大小： 1395K
代理商： MB86860
Specifications subject to changes without prior notice
29
MB86860 SPARClite
Table 5-1 Access Order between RB and WB
Access Type
hit judgment
Operation
Burst
Access
Cache Area
Store
RB: miss
Writes data to WB
OFF
(Data Access)
ASI==a,b
&
WB: miss
NC==0
RB: hit
Writes data to WB
OFF
&
WB: miss
RB: miss
Merges with that data when there is a hit to
OFF
&
initial WB data. Otherwise, writes data to WB.
WB: hit
RB: hit
Merges with that data when there is a hit to
OFF
&
initial WB data. Otherwise, writes data to WB.
WB: hit
Load
RB: miss
Reads 4 double words from external memory and writes
them
ON
ASI==a, b
&
to the RB. Simultaneously sends 1 double word to the
CPU
&
WB: miss
Core. Updates or replaces RB tags.
NC==0
RB: miss
Writes the hit data to external memory when there are
multiple
ON
&
hits or a single hit to the WB and then reads 4 double
words
WB: hit
from external memory to the RB. Simultaneously sends
1 double word to the CPU Core. Updates or replaces RB
tags.
RB: hit
Sends 1 double word from the RB to the CPU
NA
&
Core
WB: miss
RB: hit
Writes the hit data to external memory while updating the
RB
NA
&
when there are multiple hits or a single hit to the WB.
WB: hit
Thereafter sends 1 double word to the CPU Core.
Cache
Load/Fetch
IB: miss
Reads 4 double words from external memory and writes
them
ON
Area
ASI==8, 9
to the IB. Simultaneously sends 1 double word to the CPU
(instruction)
&
Core. Replaces tags
NC==0
IB: hit
Sends 1 double word to the CPU Core.
NA
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