參數(shù)資料
型號： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁數(shù)： 59/70頁
文件大?。?/td> 1395K
代理商： MB86860
Specifications subject to changes without prior notice
70
MB86860 SPARClite
(output)
SDQ<63:0>
(input/output)
O(Z)
SDRAM Data Bus.
SDQM<0:7>
(output)
O(H)
SDRAM Input Mask (Output Enable signal).
SDP<0:7>
(input/output)
O(X)
SDRAM Parity signal.
DMAC,Debug Support and Sleep Mode Signals
Pin Names
Pin Status
Explanation
Sleep
Mode
Bus
Granted
EOP#
(output)
O(V)
End of Process. The signal indicates the transfer count of DMAC reaches zero.
The EOP signal has no precise timing relation to bus cycle.
1) [Transfer from SDRAM bus to SPARClite bus]
When EOP is asserted, it is guaranteed that all SDRAM access by DMAC is completed.
2) [Transfer from SPARClite bus to SDRAM bus]
When EOP is asserted, the last access to SDRAM are still in progress.
BRKEN#
(input)
--------
Break Enable. If this signal is active ('0') at negation of RESET#, debug mode is
enabled.
DBREAK#
(input)
--------
Debug Break. Activation of the DBREAK# will cause a Debug Trap at any cycle if
DSU(Debug Support Unit) is enabled. If BRKEN# was sampled inactive at RESET# fall,
DBREAK# will not have any influence. If both DBREAK# and BRKEN# are sampled
active ('0') with RESET# fall, the MB8686X immediately jumps to Debug Trap routine
(0x00000ff0), instead of starting from 0.
BRKGO
(output)
O(V)
Break Go. This signal indicates the processor is in debug trap state. BRKGO is
asserted with the assertion of AS# for accessing Debug Trap routine and
remains active until next AS# is asserted for accessing normal program.
PDOWN#(output
)
O(L)
O(V)
Sleep Mode. This signal indicates the processor completed to enter sleep mode.
WKUP#
(input)
--------
Wake Up. Activation of the WKUP# will cause re-start of program execution. This pin
is asynchronous input. At least 2 CLKIN cycles is required for WKUP# pulse during Sleep
Mode( PDOWN#=="L" ).
STOP#
(input)
--------
Internal Clock Stop. Activation of the STOP# signal during Sleep Mode, the CPU
goes into STOP Mode and stops PLL, and all internal clocks stop.
JTAG, TEST and Other Signals
Pin Names
Pin Status
Explanation
Sleep
Mode
Bus
Granted
TDI
(input)
--------
Test Data Input. JTAG Data Input Pin. Pull-up register is required when JTAG is not
used .
TMS
(input)
--------
Test Mode Set.
JTAG Mode Set Input Pin. Pull-up register is required when JTAG is
not used .
TDO
(output)
O(X)
Test Data Output. JTAG Data Output Pin.
TCLK (input)
--------
Test Clock Input. JTAG Clock Input Pin. Pull-up register is required when JTAG is
not used .
TRST# (input)
--------
Test Reset Input. JTAG Reset Input Pin. Should normally be set to “L”.
BEN#
(input)
--------
PLL Bypass Enable. This signal can be used for test purpose only. When this signal is
“L”, PLL Bypass Mode is enabled. It should normally be fixed to “H”.
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