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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 38/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
49
MB86860 SPARClite
5.4.1.6. Internal READY Generator Function
Has the function of internally generating READY# in timing which differs from CS# to CS# in accordance with register
settings. [See the explanation of the WSPR (Reg.)]
5.4.1.7. Bus Grant Timing (BREQ# and BGRNT#)
Reads from Cache Areas (burst)
Release bus after burst transfers end.
Reads from Cache Areas (non-burst : BMACK# does not return)
Release bus after required number of single transfers.
Reads from Non-cache Areas (except ASI=8,9,a,b)
Release bus after required number of single transfers.
Atomic Load/Store
The CPU does not release external buses between Load and Store instructions of Atomic Load/Store
instructions. The CPU release a bus after a store operation (in response to an Atomic Load/Store instruction)
ends. Also, LOCK# signals are asserted during this period.
5.4.1.8. Memory Exceptions
Even though a MEXC may occur during a data transfer, the data transfer continues without pause.
MEXC# during reads
Cache Areas
Data read operations to cache areas are performed by burst transfer. If a MEXC occurs during a burst transfer
and that MEXC occurs for the first double word data of the burst transfer (data requested by the CPU -double
word, word, half word, byte- will definitely be included in the first double word access), 1 is set as a flag to bit2
of the MXPEF (Reg.). The CPU then generates a trap as an instruction access exception or a data access
exception when the burst transfer ends. MEXC occurring for the 2nd, 3rd and so forth double word data are
neither transmitted to the CPU nor stored in buffers, nor do they generate traps. However, 1 is set as a flag to
bit2 of the MXPEF (Reg.). Also, users can verify that MEXC have occurred for read operations from the CPU
or read operations from the DMAC by verifying the MXPEF (Reg.) with a trap routine.
In 32-bit, 16-bit and 8-bit Buses
MEXC# is handled in double word units for cache areas, and for other than cache areas in data type units
(double word, word, half word, byte) requested by the CPU. Thus, when a word data read is performed for 8-bit
bus width, access is performed 4 times, and if for the 1st to the 4th access MEXC# is returned together with
READY# for at least one of those accesses the CPU is notified that MEXC# has occurred for that word data
and a trap occurs.
During DMA Transfers (reads from SPARClite Bus)
When MEXC# occurs in the middle of a data read operation from a SPARClite bus while using the DMAC, 1 is
set as a flag to bit5 of the MXPEF (Reg.). A flag is also set to the ERR bit (bit7) of the MCR (Reg.). See the item
regarding DMAC Exception Processing Errors.
MEXC# during Writes
If MEXC# occur during writes, 1 is set as a flag to bit1 of the MXPEF (Reg.) for writes from the CPU and to bit5
of the MXPEF (Reg.) for writes from the DMAC. Write MEXC# are not transmitted to the CPU at the point in
time at which they occur. If 1 is set to bit0 of the MXPECR (Reg.), this is transmitted to the CPU as a MEXC
during the next read access from the CPU, and a trap occurs. If 0 (0 after Reset cancel) is set to bit0 of the
MXPECR (Reg.), MEXC is not transmitted to the CPU and no trap occurs. Accordingly, in this case the external
circuits inform the CPU of irregularities by means of interrupts. Users can verify that MEXC has occurred for a
write operation preceding a read operation by verifying the MXPEF (Reg.) with a trap routine.
5.4.1.9. Parity
Performs a Parity Check for access to the corresponding CS# areas if 1 is set to bit0 of the WSPR (Reg.).
0: Even Parity and 1: Odd Parity respectiveley depend on the value of bit1 of the MXPECR.
Bus Width and DP Pins Used
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