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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 43/70頁 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
54
MB86860 SPARClite
5.5. SS200 Bus-bridge DMAC
5.5.1. Summary
The DMAC supports flow-through transfers between SPARClite buses (SPB) and SDRAM buses. Each set register has
2 channels.
Simultaneous operation is only 1 channel.
Flow-through Transfers
SDRAM–bus <> SPARC–bus
SDRAM–bus <> SDRAM–bus
SPARC–bus <> SPARC–bus
Burst Transfer Support
Transfer Number Burst Unit (32 bytes) / set maximum 64k times (2 Mbyte)
5.5.1.1. Internal Bus Priority Order
The DMAC is connected to the chip internal BIU bus. The CPU core has BIU bus right priority. DMA transfers are
activated by setting activation bits SB of the DMA Control Registers (DMCR0, 1) to 1. When CPU Core access requests
occur during DMA operations, DMA opens a bus right in burst transfer units, and the CPU continues operating after the
bus right is opened.
5.5.1.2. Transfer Systems
The DMAC has a 64-bit 4-column FIFO and makes burst transfers of transfer length 4 (bus width 8 bytes X 4 times = 32
bytes) the basic bus cycle.
It reads 4 consecutive burst transfer data from memory spaces which indicate source
addresses and outputs 4 consecutive data in burst transfers to memory spaces indicating destination addresses. The
basic unit for transfer number settings, bus arbitration, error processing and the like is also 32 bytes. DMA transfers
basically assume non-cache space access. Since the SS200 does not support snoop functions, cache area DMA transfers
should not be performed. Memory coherency is not guaranteed during transfers.
5.5.1.3. Register Summary
Selection of respective buses for source and destination spaces, I/O area selection and CS area selection are set in the
MCR Register. I/O areas and CS areas are valid only when bus selection is specified to the SPB. CS area settings must be
set to agree with ARSR and AMR Register settings. Addresses are not updated when set to I/O areas.
Source and destination addresses are set respectively in the DMSAR and DMDAR registers. Address settings are in 32-
byte units. ASI is specified by the 4 lower order register bits. Transfer numbers are set in the DMWL Register. Transfer
numbers are set in units of 32 bytes (1 burst) to the lower order 16 bits (WL) of the register. WL indicates a 1-burst (32
bytes) transfer when 1, and transfers are possible up to a maximum of 64k bursts (2 Mbyte) at 0xf f f f. The upper order 16
bits (L WL) of the DME WL indicate the remaining number of transfers during DMA transfers or when an exception
occurs.
5.5.1.4. Activation / Termination
2 Channels can be set independently for each set DMA register. DMA activates when the start bits of all MCR Register
channels are set.
Then, after the number of transfers set to the Transfer Number Register has been executed, it
automatically clears the the Control Register start bit and stops. DMA transfers operate simultaneously in either channel
in 1 direction only. If a start bit is set in the other direction while a channel is activated in 1 direction, continuous transfers
are started in the other direction after the set number of transfers in the first direction is completed. EOP is output upon
completion of the transfers. Whether or not to output it can be specified by register settings.
5.5.1.5 Exception Processing
Aborts
If the activation bit of the MCR Register is cleared (1—> 0) during DMA transfer, DMA transfers in that channel are
aborted. Abort timing is timing in which an MCR Register clear write cycle is inserted at a break in the burst unit bus.
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