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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 57/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
67
MB86860 SPARClite
SPARClite Bus Signals (2/3)
Pin Names
Pin Status
Explanation
Sleep
Mode
Bus
Grant
BE0#~BE7#
(output)
O(Z)
Byte Enable signals. In both READ and WRITE cycle, “L” is output according
to valid byte data. In 16-bit and 8-bit bus modes, ADR<1> and ADR<0> are output
respectively to BE4# and BE5# pin. These signals are valid during bus cycle
periods.
CS0#~CS5#
(output)
O(H)
Chip Select. One of these signals are asserted when address area are accessed.
Corresponding address area are determined by the value of ARSR and AMR
registers. For detail usage, see the explanation of ARSR/AMR Registers.
In
DMAC operations, CS# signals determined by DMCR Register setting.
Also,
these signals are irrelevant during access to SDRAM areas.
DTYP< 1: 0>
(output)
O(X)
DATA TYPE. Indicates data access type (double-word, word, half-word, byte).
The output level of DTYP<1> means 11:double word, 10:word, 01:half-word and
00: byte. However, during burst transfers and cache area writes, 11 are asserted
regardless of access type.
READY#
(input)
--------
READY Input. Input “L” to this pin terminates a bus cycle. In burst transfers,
READY must be asserted a prescribed number of times for each address strobe
assert.
RDYOUT#
(output)
O(H)
Internal READY Output Signal. RDYOUT# indicates termination of bus
cycle. RDYOUT# is generated by internal wait state generator.
MEXC#
(input)
--------
Memory Access Exception. When “L” is input to this pin in the same cycle as
a READY# input, the CPU handles it as an instruction access exception or a data
access exception and generates a trap. Operations in which this signal is asserted
in timing other than the same cycle as a READY#, input are not guaranteed (Cases
where an exception occurs when the ET bit of the PSR is “0” result in error status).
For MEXC# in burst transfers, see the MEXC explanation.
BREQ#
(input)
--------
Bus Request. When this signal are asserted by an external bus master, CPU
release bus ownership to external bus master when a bunch of bus cycle are
completed. Bus release timing is as follows.
1) Burst read/write : after completion of burst access.
2) Single write/read to or from non-cache area: completion of the bus cycle.
3) Atomic LD/ST: after completion of Atomic LoadStore cycle.
4) Read/Write from 8/16/32 bit bus: after required number of single transfers.
BGRNT#
(output)
O(V)
O(L)
Bus Grant Signal. When a bus request (BREQ#) is accepted, this signal is
asserted, and external devices are notified that bus are released.
PBREQ#
(output)
O(H)
O( V)
Processor Bus Request. This signal is asserted by the processor to indicate to
an external bus arbiter on SPARClite bus that it needs to regain control of the
SPARClite bus. This provides a handshake between the arbiter and the processor
to allow the bus to allocate based on demand.
BMREQ#
(output)
O(H)
Burst Mode Request. This signal is asserted by the processor to indicate to
the external system that the current transaction can be a burst. If the external
system supports burst mode, it asserts BMACK# is concurrently with READY# to
begin the burst mode transfer.
BMACK#
(input)
--------
Burst Mode Acknowledge. This signal is asserted by the system to indicate
that it can support burst mode for the address currently on the bus. The system
asserts BMACK# in response to the processor asserting BMREQ#.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
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