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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 44/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
55
MB86860 SPARClite
After a stop because of an abort, the MCR abort bit (bit6) is set, but EOP is not output.
When the activation bit of a channel in the other direction is set, the channel in the first direction stops and a transfer is
automatically started. After the channel in the first direction has been aborted, in order not to activate a channel in the
other direction whose activation bit has been set, it is necessary to clear the activation bits of both channels. Abort bits
should be cleared by an MCR write.
Errors
If a MEXC or parity error is detected during a source data read, the DMA stops writing to destination address spaces,
and the MCR activation bit (bit0) clears both channels and stops. Also during the stop EOP is output and the ERR bit
(bit7) of the MCR is set. The ERR bit is not cleared by an MCR write. It is automatically cleared when both channels are
activated.
5.5.2. Block Diagram
Figure 5-8 SS200 DMA Block Diagram
5.6. Operating Frequencies
The SS200 has an internal clock frequency multiplier circuit which operates at 2X, 3X and 4X the external input clock.
The following shows examples of mode settings, input clocks and internal operating frequencies (maximum).
Table 5-17 Operational Frequency
Multiple
Mode
External Clock
SPARClite Bus
SDRAM Bus
SS200 Core
X
2
50MHz
100MHz
200MHz
X
3
33MHz
100MHz
200MHz
X
4
25MHz
100MHz
200MHz
address
data
Control Module
l…
Data FIFO
source address
destination address
CH0 Registers
BIU bus
CH1 Registers
DMAC
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