參數(shù)資料
型號(hào)： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 40/70頁(yè)
文件大?。?/td> 1395K
代理商： MB86860
Specifications subject to changes without prior notice
51
MB86860 SPARClite
Data Reads
If 1 is set to bit0 of the WSPR (Reg.), a Parity Check is performed, and if a Parity Error occurs, 1 is set as a flag to
bit0 of the MXPEF. It is also transmited to the CPU as MEXC. Users can verify that a Parity Error has occured
during a read by verifying bit0 of the MXPEF (Reg.) with a trap routine.
Data Writes
If 1 is set to bit0 of the WSPR (Reg.), data supporting the Parity information is output at the same time to the DP
pins during data writes.
5.4.1.10. SPARClite Bus Width and BE0#~7#
Shows data locations indicated by SPARClite Bus Width and BE0#~BE7#.
Table 6-10 Bus Width and BE0#-7#
SP-bus
DATA
width
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
64bit
D<63:56>
D<55:48>
D<47:40>
DE<39:32>
D<31:24>
D<23:16>
D<15:8>
D<7:0>
32bit
-------------
D<31:24>
D<23:16>
D<15:8>
D<7:0>
16bit
-------------
*1 ADR<1>
*1 ADR<0>
D<15:8>
D<7:0>
8bit
-------------
*1 ADR<1>
*1 ADR<0>
-------------
D<7:0>
During reads from cache areas and DMAC read operations, BE0#~7# are all asserted.
Only BE is asserted to valid bytes during read operations other than the above.
Only BE is asserted to valid bytes during writes.
The above support is the same in both Big-Endian and Little-Endian operations.
NOTE *1 : In 16-bit and 8-bit Bus Width ADR<1:0> is output to BE4# and BE5#.
5.4.2. SPARClite Bus Operations
Figure 5-1 SPARClite Non-Burst Read/Write Operations
CLKIN
Data Buffer
Non-Burst read
Data
Buffer/DMAC
Idle
Cycle
AS#
RD#
RDWR#
ASI[3:0]
ADR[31:2]
D[63:0]
BE0#~BE7#
CSx#
DTYP[1:0]
READY#
X
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