參數(shù)資料
型號： MB86860
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： PLASTIC, BGA-352
文件頁數(shù)： 46/70頁
文件大小： 1395K
代理商： MB86860
Specifications subject to changes without prior notice
57
MB86860 SPARClite
6.
Debug Support Unit (DSU)
6.1. DSU Features
The 3 Types of Debug Trap Conditions
— Items which depend on external input (DBREAK#) (asynchronous)
— Internal hardware break points (instruction address conveyors, single step mode)
— Software break points (
TA255)
Debug Mode by sampling when resetting the BRKEN# pin
Debug Support Registers
— 2 instruction address descriptor registers (IADR1, IADR2)
— Debug
control registers (DCR)
— Debug
status registers (DSR)
SPARClite and Program Models are identical
— Debug
Support Register addresses are the same as SPARClite
— All SPARClite DSR and DCR bits are not implemented, but those which are implemented are the same.
Debugging is possible only in Supervisor Mode.
Debug Trap Features
— All debug trap types are 255, and TBA is ignored.
–>Debug traps always start at address 0x00000ff0.
— Debug trap priority is 2 (highest rank except for reset)
— Debug traps are not masked by PSR ET=0.
— Flags exclusively for new debug routines (pET, pPS)
ROM (or FLASH ROM) for debug trap routines can be selected by external pin (BRKGO) which indicates
debug status.
The Debug Support Unit stops operating in Normal Mode to reduce power consumption.
The PC trace function has a 16-column buffer, and it saves instruction addresses from the program counter.
6.2. DSU Functions
6.2.1. Move to Debug Mode
The CPU has 2 statuses: Debug Mode and Normal Mode. The EN_BRK_ bit of the DSR Register indicates the current
mode.
EN_BRK_ = 0 . . . Debug Mode
EN_BRK_ = 1 . . . Normal Mode
The mode is decided by BRKEN# pin status when a reset signal is canceled. Values at this time are stored in the
EN_BRK_ pin and cannot be rewritten by the software until the next reset. In Normal Mode all breaks are disabled and
debug traps are not activated. In addition, the DSU stops functioning in order to reduce power consumption.
Upon reset, if the DBREAK# and BRKEN# pins are asserted simultaneously, instead of fetching instructions from CPU0
addresses they jump immediately to a debug trap routine (0x00000FF0). In this way the boot ROM can be replaced by a
debug monitor. By using the SWF bit (in the DCR Register), the software can decide whether or not that debug trap
routine was activated immediately following a reset. Since the SWF bit is “0” immediately following a reset, if “1” is
written at that time, and this bit is read when the next debug routine is activated, it becomes clear that the routine was
not activated immediately following a reset if that bit is “1”.
6.2.2. Debug Trap Activation
There are 3 ways of activating debug traps:
1.
Activation by External Break Pins
The EB bit of the DSR Register is set by DREAK# fall input, and an asynchronous debug trap activates. This input
is ignored between Normal Mode and debug trap routines.
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