
2-86
7/9/98
Timers
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Each time the Timer Y underflows, the output of the CNTR1 pin is inverted, and the corresponding
Timer Y interrupt request bit is set to a “1”. The repeated inversion of the CNTR1 pin output
produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is
determined by the CNTR1 polarity select bit (bit 6). When this bit is low, the output starts from a
high level. When this bit is high, the output starts from a low level.
2.13.2.4
Pulse Period Measurement Mode
Φ
/
n
(where
n
is 8, 16, 32, or 64).
Count Source:
This mode measures the period of the event waveform input to the CNTR1 pin.
CNTR1 Polarity Select Bit (TYM6) = “0”
When the falling edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned the same address as Timer Y. Simultaneously, the
value in the Timer Y reload latch is transferred to Timer Y, and Timer Y continues counting down.
The falling edge of an event waveform also causes the CNTR1 interrupt request; therefore, the period
of the event waveform from falling edge to falling edge is found by reading Timer Y in the CNTR1
interrupt routine. The data read from Timer Y is the data previously stored in its temporary register.
CNTR1 Polarity Select Bit (TYM6) = “1”
When the rising edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned the same address as Timer Y. Simultaneously, the
value in the Timer Y reload latch is transferred to Timer Y, and Timer Y continues counting down.
The rising edge of an event waveform also causes the CNTR1 interrupt request; therefore, the period
of the event waveform from rising edge to rising edge is found by reading Timer Y in the CNTR1
interrupt routine. The data read from Timer Y is the data previously stored in its temporary register.
Each time the timer underflows, the Timer Y interrupt request bit is set to a “1”, the contents of
the timer reload latch are loaded into the timer, and the countdown sequence begins again.
2.13.2.5
Event Counter Mode
Count Source:
CNTR1
Timer countdown is triggered by input to the CNTR1 pin. Each time a timer underflows, the
corresponding timer interrupt request bit is set to a “1”, the contents of the timer reload latch are
loaded into the timer, and the countdown sequence begins again.
The edge used to clock Timer Y is determined by the CNTR1 polarity select bit (bit 6). When these bits
are “0”s, the timers are clocked on the rising edge. When these bits are “1”s, the timers are clocked on the
falling edge
2.13.2.6
HL Pulse-width Measurement Mode
Φ
/
n
(where
n
is 8, 16, 32, or 64).
Count Source:
This mode continuously measures both the logical high pulse width and the logical low pulse width of an
event waveform input to the CNTR1 pin. When the falling (or rising) edge of the event waveform is
detected on the CNTR1 pin, the contents of Timer Y are stored in the temporary register that is assigned the
same address as Timer Y, regardless of the setting of the CNTR1 polarity select bit. Simultaneously, the
value in the Timer Y reload latch is transferred to Timer Y, which continues counting down. The falling or
rising edge of an event waveform causes the CNTR1 interrupt request; therefore, the width of the event
waveform from the falling or rising edge to rising or falling edge is found by reading Timer Y in the
CNTR1 interrupt routine. The data read from Timer Y is the data previously stored in its temporary register.