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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁數(shù)： | 106/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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2-94
7/9/98
UART
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.14.3 UART Control Register
The UxCON specifies the initialization and enabling of a transmit/receive process (see Figure 2-110).
Data can be read from and written to the Control Register.
Figure 2-110. UxCON Register
2.14.4 UART Baud Rate Register
In the UART Baud Rate Register (UxBRG), any value can be specified to obtain the desired baud
rate. This register remains in effect whether the UART state is send-enabled, receive-enabled, transmit-
in-progress, or receive-in-progress. The contents of this register can be modified only when the UART
is not in any of these four states.
2.14.5 UART Status Register
The UART Status Register (UxSTS) reflects both the transmit and receive status (see Figure 2-111).
The status register is read only. The MSB is always “0” during a read operation. Writing to this
register has no effect. Status flags are set and reset under the conditions indicated below. The setting
and resetting of the transmit and receive status are not affected by transmit and receive enable flags.
The setting and resetting of the receive error flags and receive buffer full flag differs when UART
address mode is enabled. These differences are described in section “2.14.9 UART Address Mode”.
Receive Error Sum Flag
The Receive Error Sum Flag (SER) is set when an overrun, framing, or parity error occurs after
completion of a receive operation.
It is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized
by setting the Receive Initialization Bit (RIN). If the receive operation completes while the status
register is being read, the status information is updated upon completion of the status register read.
MSB
7
LSB
0
AME
TIS
RIN
REN
TEN
TEN
Transmission Enable Bit (bit 0)
0: Disable the transmit process
1: Enables the transmit process. If the transmit process is disabled (TEN cleared)
during transmission, the transmit will not stop until completed.
Receive Enable Bit (bit 1)
0: Disable the receive process
1: Enables the receive process. If the receive process is disabled (REN cleared)
during reception, the receive will not stop until completed.
Transmission Initialization Bit (bit 2)
0: No action.
1: Resets the UART transmit status register bits as well as stopping the transmission
operation. The TEN bit must be set and the transmit buffer reloaded in order to transmit
again. The TIN is automatically reset one cycle after TIN is set.
Receive Initialization Bit (bit 3)
0: No action.
1: Clears the UART receive status flags and the REN bit. If RIN is set during receive in
progress, receive operation is aborted. The RIN bit is automatically reset one cycle
after RIN is set.
Transmit Interrupt Source Selection Bit (bit 4)
0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
1: Transmit interrupt occurs when the Transmit Complete flag is set.
Clear-to-Send (CTS) Enable Bit (bit 5)
0: CTS function is disabled, P8
6
(or P8
2
) is used as GPIO pin.
1: CTS function is enabled, P8
(or P8
2
) is used as CTS input.
Request-to-Send (RTS) Enable Bit (bit 6)
0: RTS function is disabled, P8
7
(or P8
3
) is used as GPIO pin.
1: RTS function is enabled, P8
(or P8
3
) is used as RTS output.
UART Address Mode Enable Bit (bit 7)
0: Address Mode disabled.
1: Address Mode enabled.
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Access: R/W
Reset: 00
16
RTS_SEL
CTS_SEL
TIN
Address: 0033
16
,003B
16
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