參數(shù)資料
型號(hào)： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 41/172頁
文件大?。?/td> 1193K
代理商： M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Input and Output Ports
7/9/98
2-29
At reset, all of the direction registers are initialized to 00
16
, setting all of the I/O ports to input mode.
If data is written to a pin and then read from that pin while it is in output mode, the data read is the
value of the port latch rather than the value of the pin itself. Therefore, if an external load changes the
value of an output pin, the intended output value will still be read correctly. Pins set to input mode
are floating (provided that the pull up resistors are not being used) to ensure that the value input to
such a pin can be read accurately. In the case when data is written to a pin configured as an input,
the data is written only to the port latch; the pin itself remains floating.
Most of the I/O Ports are multiplexed with secondary functions. When a GPI/O is multiplexed with a
second function, the control signal from the peripheral overrides the direction register. The
multiplexing is briefly described below. The second function signals to and from the I/O ports are
described in detail in their respective block's description.
2.7.1.1
I/O Ports
Ports 0, 1, and 3
Ports 0 and 1 act as the address bus (AB
0
-AB
15
) in Microprocessor and Memory Expansion modes.
Bits 0 and 3-7 of Port 3 acts as control signals in Microprocessor and Memory Expansion modes.
Figure 2-26. Port P0, P1, and P3 Block Diagram
Port 2
Port 2 is an 8-bit general purpose I/O port when in single chip mode. In this mode, the port has
key-on wake up circuitry which can be used to restart the chip externally from a WIT or STP low
power mode. This port also acts as the data bus during microprocessor and memory expansion
modes. Port 2 input level can be set to reduced VIHL level or CMOS level by bit 6 of the port
control register (PTC).
Figure 2-27. Port P2 Block Diagram
Direction Register
Data Bus
Port Latch
Direction Register
Pull-up Control
Data Bus
Port Latch
Key-on Wake-up Input
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