5-12
6/2/98
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Figure 5-24. DMAIS Configuration
Figure 5-25. DMAxM1 Configuration
D0UF
DMAC Channel 0 Count Register Underflow Flag (bit 0)
0: Channel 0 transfer count register underflow has not occurred
1: Channel 0 transfer count register underflow has occurred
DMAC Channel 0 Suspend (due to interrupt service request) Flag (bit 1)
0: Channel 0 transfer has not been suspended
1: Channel 0 transfer has been suspended
DMAC Channel 1 Count Register Underflow Flag (bit 2)
0: Channel 1 transfer count register underflow has not occurred
1: Channel 1 transfer count register underflow has occurred
DMAC Channel 1 Suspend (due to interrupt service request) Flag (bit 3)
0: Channel 1 transfer has not been suspended
1: Channel 1 transfer has been suspended
DMAC Transfer Suspend Control Bit (bit 4)
0: Only burst transfers are suspended during interrupt servicing
1: Both burst and single-byte transfers are suspended during interrupt servicing
DMAC Register Reload Disable Bit (bit 5)
0: Reload of source and destination registers of both channels enabled
1: Reload of source and destination registers of both channels disabled
Reserved (Read/Write “0”)
Channel Index Bit (bit 7)
0: Channel 0 mode, source, destination, and transfer count registers accessible
1: Channel 1 mode, source, destination, and transfer count registers accessible
D0SFI
D1UF
D1SFI
DTSC
DRLDD
Bit 6
DCI
MSB
7
LSB
0
DCI
Reserved
DRLDD
DTSC
D1SFI
D1UF
D0SFI
D0UF
Access: R/W
Reset: 00
16
Address: 003F
16
MSB
7
LSB
0
DxTMS
DxRLD
DxDAUE
DxDWC
DxDRCE
DxDRID
DxSRCE
DxSRID
DxSRID
DMAC Channel x Source Register Increment/Decrement Select Bit (bit 0)
0: Increment after transfer
1: Decrement after transfer
DMAC Channel x Source Register Increment/Decrement Enable Bit (bit 1)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC Channel x Destination Register Increment/Decrement Select Bit (bit 2)
0: Increment after transfer
1: Decrement after transfer
DMAC Channel x Destination Register Increment/Decrement Enable Bit (bit 3)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC Channel x Data Write Control Bit (bit 4)
0: Write data in reload latches and registers
1: Write data in reload latches only
DMAC Channel x Disable After Count Register Underflow Enable Bit (bit 5)
0: Channel x not disabled after count register underflow
1: Channel x disabled after count register underflow
DMAC Channel x Register Reload Bit (bit 6)
0: No action (Bit is always read as “0”)
1: Setting to “1” causes the source, destination, and transfer count registers
of channel x to be reloaded
DMAC Channel x Transfer Mode Selection Bit (bit 7)
0: Single-byte transfer mode
1: Burst transfer mode
DxSRCE
DxDRID
DxDRCE
DxDWC
DxDAUE
DxRLD
DxTMS
Access: R/W
Reset: 00
16
Address: 0040
16