2-54
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MAXP > half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the host. The CPU writes a “0” to the
OUT_PKT_RDY bit after the packet of data is unloaded from the OUT FIFO by the CPU/DMAC.
MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the host. The CPU writes a “0” to the
OUT_PKT_RDY bit after the packet of data is unloaded from the OUT FIFO by the CPU/DMAC. In
this configuration, the FIFO can hold upto two data packets at the same time, for back-to-back
reception. Therefore, the OUT_PKT_RDY bit may remain set after the CPU writes a “0” to it if there
is another packet in the OUT FIFO.
Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of OUT CSR) = “1”
:
MAXP > half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY
bit to a ‘0’ automatically when the number of bytes of data equal to the MAXP (maximum packet
size) is unloaded from the OUT FIFO by the CPU/DMAC.
MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY
bit to a “0” automatically when the number of bytes of data equal to the MAXP (maximum packet
size) is unloaded from the OUT FIFO by the CPU/DMAC. In this configuration, the FIFO can hold up
to two data packets at the same time, for back-to-back reception. Therefore, the OUT_PKT_RDY bit
may remain set after one packet (size equal to MAXP) of data is unloaded if there is another packet
in the OUT FIFO.
A software flush acts as if a packet is being unloaded from the OUT FIFO. If there is one packet in
the OUT FIFO, a flush will cause the OUT FIFO to be empty, if there are two packets in the OUT
FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO.
Special case for OUT endpoint 1
: In addition to the OUT FIFO operations described above, the
DMAC can also start unloading the OUT FIFO as soon as there is data in it (byte-by-byte transfer).
This feature should only be used with ISO transfers. See section 2.11 "Direct Memory Access
Controller" on page 2-69 for details.
2.9.4
USB Special Function Registers
The MCU controls USB operation through the use of special function registers (SFR). This section
describes in detail each USB related SFR. Certain USB SFRs are endpoint-indexed: the Control &
Status Registers (IN CSR and OUT CSR), the Maximum Packet Size Registers (IN MAXP and OUT
MAXP), and the Write Count Registers (OUT WRT CNT). To access each endpoint-indexed SFR, the
target endpoint number should be written to the Endpoint Index Register first. The lower 3 bits
(EPINDX2:0) of the Endpoint Index Register are used for endpoint selection.
Note:
Each endpoint’s FIFO Register is NOT endpoint-indexed.
Some USB special function registers have a mix of read/write, read only, and write only register bits.
Additionally, the bits may be configured to allow the user to write only a “0” or a “1” to individual
bits. When accessing these registers, writing a “0” to a register that can only be set to a “1” by the
CPU will have no affect on that register bit. Each figure and description of the special function
registers will detail this operation.
The
USB Control Register,
shown in Figure 2-64
,
is used to control the USB FCU. This register is
not reset by a USB reset signaling. After the USB is enabled (USBC7 set to “1”), a minimum delay
of 250 ns (three 12Mhz clock periods) is needed before performing any other USB register read/write
operations.