
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Universal Serial Bus
7/9/98
2-59
IN0CSR0
(OUT_PKT_RDY): The USB FCU sets this bit to a “1” upon receiving a valid SETUP/OUT
token from the host. The CPU clears this bit after unloading the FIFO, by way of writing a “1” to
IN0CSR6. The CPU should not clear the OUT_PKT_RDY bit before finishes decoding the host request. If
IN0CSR2 (SEND_STALL) needs to be set - the CPU decodes an invalid or unsupported request - the
setting IN0CSR6 = “1” & IN0CSR2 = “1” should be done in a same CPU write.
IN0CSR1
(IN_PKT_RDY): The CPU writes a “1” to this bit after finishes writing a packet of data to
the endpoint 0 FIFO. The USB FCU clears this bit after the packet is successful transmitted to the
host, or the IN0CSR5 (SETUP_END) bit is set.
IN0CSR2
(SEND_STALL): The CPU writes a “1” to this bit if it decodes an invalid or unsupported
standard device request from the host. The USB FCU returns a STALL handshake for all subsequent
IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes
a “0” to clear this bit.
IN0CSR3
(DATA_END): For control transfers, the CPU writes a “1” to this bit when it writes (IN
data phase) or reads (OUT data phase) the last packet of data from/to the FIFO. This bit indicates to
the USB FCU that the specific amount of data in the setup phase is transferred. The USB FCU will
advance to the status phase once this bit is set. When the status phase completes, the USB FCU clears
this bit. When this bit is set to a “1”, and the host again requests or sends more data, the USB FCU
will return a STALL handshake.
IN0CSR4
(FORCE_STALL): The USB FCU sets this bit to a “1” if the host sends out a larger data
packet than the MAXP size, or if during a data stage a command pipe is sent more data or is
requested to return more data than was indicated in the setup stage (also see description for IN0CSR3).
The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during data or
status stages) while this bit is set. The CPU writes a “0” to clear this bit.
IN0CSR5
(SETUP_END): The USB FCU sets this bit to a “1” if a control transfer has ended before
the specific length of data is transferred during the data phase. The CPU clears this bit by way of
writing a “1” to IN0CSR7. Once the CPU sees the SETUP_END bit set, it should stop accessing the
FIFO to service the previous setup transaction. If OUT_PKT_RDY is set at the same time
SETUP_END is set, it indicates the previous setup transaction ended, and a new SETUP token is in
the FIFO.
IN0CSR6
and
IN0CSR7
: These bits are used to clear IN0CSR0 and IN0CSR5 respectively. Writing a “1”
to these bits will clear the corresponding register bit.