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參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機 |
| 文件頁數(shù)： | 64/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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2-52
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
The Over/Underrun status bit is set (applicable to endpoints used for isochronous data transfer), when
an overrun condition occurs in an endpoint (CPU is too slow to unload the data from the FIFO), or
when an underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO).
The USB Function Interrupt (sum of all individual function interrupts) is enabled by setting the
corresponding bit in the Interrupt Control Register of the Interrupt Control Unit.
2.9.2.2
USB SOF Interrupt
The USB SOF (Start-Of-Frame) interrupt is used to control the transfer of isochronous data. The USB
FCU generates a start-of-frame interrupt when a start-of-frame packet is received. The USB SOF
interrupt is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt
Control Unit.
2.9.3
USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Both FIFOs
support up to two separate data sets of variable size (except Endpoint 0), and provide the ability of
back-to-back transmission and reception. Throughout this specification, the terms “IN FIFO” and “OUT
FIFO” refer these FIFOs associated with the current endpoint as specified by the Endpoint Index
Register.
In the event of a bad transmission/reception, the USB FCU handles all the read/write pointer reversal
and data set management tasks when it is applicable.
2.9.3.1
IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint’s IN FIFO location specified by the FIFO write pointer,
which automatically increments by "1" after a write. The CPU/DMA should only write data to the IN
FIFO if the IN_PKT_RDY bit of the IN CSR is a “0”.
Endpoint 0 IN FIFO Operation
: The CPU writes a “1” to the IN_PKT_RDY bit after it finishes
writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet
is successfully transmitted to the host (ACK is received from the host) or the SETUP_END bit of the
IN CSR is set to a “1”.
Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = “0”
:
MAXP > half of the IN FIFO size: The CPU writes a “1” to IN_PKT_RDY bit after the CPU/DMAC
finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the
packet is successfully transmitted to the host (ACK is received from the host).
MAXP <= half of the IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit after the CPU/
DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit
as soon as the IN FIFO is ready to accept another data packet (The FIFO can hold up to two data
packets at the same time in this configuration, for back-to-back transmission). Since the set and the
clear operations could be as fast as 83ns (one 12MHz clock period) apart from each other, the set may
be transparent to the user.
Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = “1”
:
MAXP > half of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum
packet size) is written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit
to a ‘1’ automatically. The USB FCU clears the IN_PKT_RDY bit after the packet is successfully
transmitted to the host (ACK is received from the host).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M37640M4T | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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