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參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機 |
| 文件頁數(shù)： | 20/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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2-8
7/9/98
Oscillator Circuit
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.3
Oscillator Circuit
2.3.1
Description
An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for
operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for
oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. A
flow diagram for the oscillator circuit is shown in Figure 2-6 and a block diagram of the oscillator
circuit is shown in Figure 2-7. The following external clock inputs are supported:
A quartz crystal oscillator of up to 24 MHz, connected to the X
in
and X
out
pins.
An external clock signal of up to 48 MHz, connected to the X
in
pin.
A ceramic resonator or quartz crystal oscillator of 32.768 kHz, connected to the XC
in
and XC
out
pins.
An external clock signal of up to 5.12 MHz, connected to the XC
in
pin.
The frequency synthesizer can be used to generate a 48MHz clock signal (f
USB
) needed by the USB
block and clock f
SYN
, which can be chosen as the source for the system and peripheral clocks. Both
f
USB
and f
SYN
are phase-locked frequency multiples of the frequency synthesizer input. The inputs to
the frequency synthesizer can be either X
in
or XC
in
.
The two-phase non-overlapping system clock (CPU and peripherals) is derived from the source to the
clock circuit and is 1/2 the frequency of the source. (i.e. Source = 24 MHz, system clock = 12 MHz)
Any one of four clock signals can be chosen as the source for the system and peripheral clocks; f
Xin
/
2, f
Xin
, f
XCin
, or f
SYN
. The selection is based on the values of bits CPMA6, CPMA7 and CCR7. The
default source after reset is f
Xin
/2.
The default source for the system and peripheral clocks is f
Xin
/2. If f
Xin
= 24MHz, then the CPU
will be running at
Φ
= 6MHz (low frequency mode. For the CPU to run in high frequency mode, i.e.,
source of clock = f
Xin
, write a “1” to bit 7 of the clock control register.
Figure 2-5. Clock Control Register
The drive strength of the X
out
and XC
out
inverting amplifier can be controlled by bits CPMB7 and
CPMA3, respectively. High drive is the default at reset or after executing a STP instruction and must
be chosen whenever restarting X
in
or XC
in
oscillation if a ceramic or crystal oscillator is used. When
oscillation has been established, low drive can be selected to reduce power consumption. If an
external clock signal is input to X
in
or XC
in
, the inverting amplifiers can be disabled by means of the
CCR6 and CCR7 bits, respectively, in order to reduce power consumption.
Bits 0-3
CCR4:
Reserved (Read/Write “0”)
PLL Bypass Bit (bit 4)
0: f
USB
= f
VCO
(Frequency synthesizer output)
1: f
= f
XC
Oscillation Drive Disable Bit (bit 5)
0: XC
out
oscillation drive is enabled (when XC
in
oscillation is enabled).
1: XC
oscillation drive is disabled.
X
out
Oscillation Drive Disable Bit (bit 6)
0: X
out
oscillation drive is enabled (when X
in
oscillation is enabled).
1: X
oscillation drive is disabled.
X
in
Divider Select Bit (bit 7)
0: f
Xin
/2 is used for the system clock source when CMPA7:6=00
1: f
Xin
is used for the system clock source when CMPA7:6=00
CCR5:
CCR6:
CCR7:
MSB
7
LSB
0
Reserved
Reserved
Reserved
Access: R/W
Reset: 00
16
Reserved
Address: 001F
16
CCR4
CCR7
CCR6
CCR5
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