參數資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機
文件頁數: 68/172頁
文件大小: 1193K
代理商: M37640E8
2-56
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Figure 2-66. USB Power Management Register
The USB FCU is able to generate a USB function interrupt as discussed in section 2.9.2.1. The
USB
Interrupt Status Registers,
shown in Figure 2-67 and Figure 2-68, are used to indicate the condition
that caused a USB function interrupt to the CPU. A “1” indicates the corresponding condition caused a
USB function interrupt. The USB Interrupt Status Registers can be cleared by writing back to the
register the same value that was read. To ensure proper operation, the CPU should read both USB
interrupt status registers, then write back the same values it read to these two registers for clearing the
status bits. The CPU must write the USB Interrupt Status Register 1 first, then the USB Interrupt
Status Register 2. The registers cannot be cleared by writing a “0” to the bits that are a “1”.
The
USB Interrupt Enable Registers,
shown in Figure 2-69 and Figure 2-70, are used to enable the
corresponding interrupt status conditions, which can generate a USB function interrupt. If the bit to a
corresponding interrupt condition is “0”, that condition will not generate a USB function interrupt. If
the bit is a “1”, that condition can generate a USB function interrupt. Upon reset, all USB interrupt
status conditions are enabled except bit 7 of USB Interrupt Enable Register 2 - i.e., suspend and
resume interrupt is disabled.
Figure 2-67. USB Interrupt Status Register 1
INTST0
is set to a “1” by the USB FCU if (in Endpoint 0 IN CSR):
Successfully receives a packet of data
Successfully sends a packet of data
IN0CSR3 (DATA_END) bit is cleared
IN0CSR4 (FORCE_STALL) bit is set
IN0CSR5 (SETUP_END) bit is set
INTST2
,
INTST4
,
INTST6
or
INTST8
is set to a “1” by the USB FCU if (in Endpoint x IN CSR):
Successfully sends a packet of data
INXCSR1 (UNDER_RUN) bit is set
SUSPEND
USB Suspend Detection Flag (bit 0) (Write “0” only or Read)
0: No USB suspend signal detected
1: USB suspend signal detected
USB Resume Detection Flag (bit 1) (Write “0” only or Read)
0: No USB resume signal detected
1: USB resume signal detected
USB Remote Wake-up Bit (bit 2)
0: End remote resume signaling
1: Remote resume signaling (If SUSPEND = “1”)
RESUME
WAKEUP
Bit7:3
Reserved (Read/Write “0”)
MSB
7
LSB
0
Reserved
Reserved
Reserved
Reserved
Reserved
RESUME SUSPEND
Access: R/W
Reset: 00
16
WAKEUP
Address: 0051
16
INTST0
USB Endpoint 0 Interrupt Status Flag (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
USB Endpoint 1 IN Interrupt Status Flag (bit 2)
USB Endpoint 1 OUT Interrupt Status Flag (bit 3)
USB Endpoint 2 IN Interrupt Status Flag (bit 4)
USB Endpoint 2 OUT Interrupt Status Flag (bit 5)
USB Endpoint 3 IN Interrupt Status Flag (bit 6)
USB Endpoint 3 OUT Interrupt Status Flag (bit 7)
0: No interrupt request issued
1: Interrupt request issued
MSB
7
LSB
0
INTST7
INTST6
INTST5
INTST4
INTST3
Reserved
INTST0
Access: R/W
Reset: 00
16
INTST2
Address: 0052
16
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