參數(shù)資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機(jī)
文件頁數(shù): 107/172頁
文件大?。?/td> 1193K
代理商: M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
UART
7/9/98
2-95
Receive Overrun Flag
The Receive Overrun Flag (OER) is set if the previous data in the low-order byte of the receive buffer
(UxTRB1) is not read before the current receive operation is completed. It is also set if a receive error
occurred for the previous data and the status register is not read before the current receive operation is
completed. This flag is reset when the status register is read. This flag is also reset when the hardware
reset is asserted or the receiver is initialized by RIN. If the receive operation completes while the
status register is being read, the status information is updated upon completion of the status register
read.
Receive Framing Error Flag
The Receive Framing Error Flag (FER) is set when the stop bit of the received data is “0”. If the
Stop Bit Selection Bit (STB, bit 3 of UxMOD) is set, the flag is set if either of the two stop bits is a
“0”. This flag is reset when the status register is read, the hardware reset is asserted, or the receiver is
initialized by RIN. If the receive operation completes while the status register is being read, the status
information is updated upon completion of the status register read.
Receive Parity Error Flag
The Receive Parity Error Flag (PER) is set when the parity of received data and the Parity Selection
Bit (PMD, bit 4 of UxMOD) are different. It is enabled only if the Parity Enable Bit (PEN, bit 5 of
UxMOD) is set.
This flag is reset when the status register is read, the hardware reset is asserted, or the receiver is
initialized by RIN. If the receive operation completes while the status register is being read, the status
information is updated upon completion of the status register read.
Receive Buffer Full Flag
The Receive Buffer Full Flag (RBF) is set when the last stop bit of the data is received. It is not set
when a receive error occurs. This flag is reset when the low-order byte of the receive buffer
(UxTRB1) is read, the hardware reset is asserted, or the receive process is initialized by RIN. If the
receive operation completes while the status register is being read, the status information is updated
upon completion of the status register read.
Transmission Complete Flag
In the case where no data is contained in the transmit buffer, the Transmission Complete Flag (TCM)
is set when the last bit in the transmit shift register is transmitted. In the case where the transmit
buffer does contain data, the TCM flag is set when the last bit in the transmit shift register is
transmitted if TBE is a “0” or CTS handshaking is enabled and CTSx is “1”. The TCM flag is also
set when the hardware reset is asserted or when the transmitter is initialized by setting the Transmit
Initialization Bit (TIN, bit 2 of UxCON). It is reset when a transmission operation begins.
Transmission Buffer Empty Flag
The Transmission Buffer Empty Flag (TBE) is set when the contents of the transmit buffer are loaded
into the transmit shift register. The TBE flag is also set when the hardware reset is asserted or when
the transmitter is initialized by TIN. It is reset when a write operation is performed to the low-order
byte of the transmit buffer (UxTRB1).
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