
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Master CPU Bus Interface
7/9/98
2-67
Figure 2-90. Data Bus Buffer Control Register 0
Figure 2-91. Data Bus Buffer Status Register 1
Figure 2-92. Data Bus Buffer Control Register 1
DBBC00
OBF Output Selection Bit (bit 0)
0: P5
2
pin is operated as GPIO
1: P5
pin is operated as OBF
0
output pin
IBF Output Selection Bit (bit 1)
0: P5
3
pin is operated as GPIO
1: P5
pin is operated as IBF
0
output pin
IBF
Interrupt Selection Bit (bit 2)
0: IBF
0
interrupt is generated by both write-data (A
0
= “0”) and write-command (A
0
= “1”)
1: IBF
interrupt is generated by write-command (A
0
= “1”) only
Output buffer 0 empty interrupt disable Bit (bit 3)
0: Enabled
1: Disabled
Input buffer 0 full interrupt disable Bit (bit 4)
0: Enabled
1: Disabled
Reserved (Read/Write “0”)
Master CPU Bus Interface Enable Bit (bit 6)
0: P6
0
-P6
7
, P5
4
-P5
7
are GPIO pins
1: P6
-P6
, P5
-P5
are bus interface signals DQ0-DQ7, S
0
, A
0
, R, W respectively.
Bus Interface Type Selection Bit (bit 7)
0: RD, WR separate type bus
1: R/W type bus.
DBBC01
DBBC02
DBBC03
DBBC04
DBBC05
DBBC06
DBBC07
MSB
7
LSB
0
DBBC06
DBBC01
DBBC00
Access: R/W
Reset: 00
16
DBBC02
DBBC07
Address: 004A
16
DBBC03
DBBC04
Reserved
MSB
7
LSB
0
DBBS16
DBB15
DBBS14
DBBS13
DBBS11
DBBS10
DBBS10
Output Buffer Full (OBF
1
) Flag (bit 0)
0: Output buffer empty.
1: Output buffer full.
Input Buffer Full (IBF
) Flag (bit 1)
0: Input buffer empty.
1: Input buffer full.
User Definable (U2) Flag (bit 3)
A
0
(A
) Flag (bit 2)
Indicates the A
status when IBF flag is set
User Definable (U4) Flag (bit 4)
User Definable (U5) Flag (bit 5)
User Definable (U6) Flag (bit 6)
User Definable (U7) Flag (bit 7)
DBBS11
DBBS12
DBBS13
DBBS14
DBBS15
DBBS16
DBBS17
Access: R/W
Reset: 00
16
DBBS12
DBBS17
Address: 004D
16
DBBC10
OBF
Output Selection Bit (bit 0)
0: P7
4
pin is operated as GPIO
1: P7
pin is operated as OBF
1
output pin if DBBC17 = “1”
IBF
Output Selection Bit (bit 1)
0: P7
3
pin is operated as GPIO
1: P7
pin is operated as IBF
1
output pin if DBBC17 = “1”
IBF
Interrupt Selection Bit (bit 2)
0: IBF
1
interrupt is generated by both write-data (A
0
= “0”) and write-command (A
0
= “1”)
1: IBF
interrupt is generated by write-command (A
0
= “1”) only
Output Buffer 1 Empty interrupt disable Bit (bit 3)
0: Enabled
1: Disabled
Input Buffer 1 Full interrupt disable Bit (bit 4)
0: Enabled
1: Disabled
Reserved (Read/Write “0”)
Reserved (Read/Write “0”)
Data Bus Buffer Function Selection Bit (bit 7)
0: Single data bus buffer - P7
2
is used as GPIO
1: Double data bus buffer - P7
2
is used as S
1
input
DBBC11
DBBC12
DBBC13
DBBC14
DBBC15
DBBC16
DBBC17
MSB
7
LSB
0
DBBC11
DBBC10
Access: R/W
Reset: 00
16
DBBC12
DBBC17
Address: 004E
16
Reserved
DBBC13
DBBC14
Reserved