參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 110/172頁
文件大?。?/td> 1193K
代理商： M37640E8
2-98
7/9/98
UART
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
detected, the contents of the receive shift register are transferred to the receive buffer and the
Receive Buffer Full Flag in the UxSTS is set to a “1”, if a receive error has not occurred. The
RBF interrupt request is also generated at this time if a receive error has not occurred. However,
if a receive error did occur, the appropriate error flags are set and the Receive Error Sum (SER)
interrupt request is generated at this time.
When the low-order byte of the receive buffer (UxTRB1) is read, the Receive Buffer Full Flag is
cleared, and the receive buffer is now ready for the next byte. If 9-bit character length has been
selected, the high-order byte of the receive buffer (UxTRB2) should be read before reading the
low-order byte (UxTRB1).
Figure 2-113. UART Receive Operation Waveforms
2.14.7 Interrupts
The transmit and receive interrupts are generated under the conditions described below. The generation
of the receive interrupts differs when UART Address mode is enabled. The differences are described in
section “2.14.9 UART Address Mode”.
Transmit interrupts
The UART generates a Transmit interrupt to the CPU core. The source of the Transmit interrupt is
selectable by setting TIS.
If TIS = “0”, the Transmit interrupt is generated when the transmit buffer register becomes empty
(that is, when TBE flag set).
If TIS = “1”, the Transmit interrupt is generated after the last bit is sent out of the transmit shift
register and no data has been written to the transmit buffer or CTS handshaking is enabled and
CTSx is high (that is, when TCM flag set).
Receive Interrupts
The UART generates the Receive Buffer Full (RBF) and Receive Error Sum (SER) interrupts to the
CPU core when receiving.
The RBF interrupt is generated when a receive operation completes and a receive error is not
generated.
The SER interrupt is generated when an overrun, framing or parity error occurs.
UxBRG
Clock
URXDx
RBF
Start bit
D0
Stop bit
Start bit
D0
Edge
detection
2-of-3
sampling
2-of-3
sampling
2-of-3
sampling
2-of-3
sampling
2-of-3
sampling
Edge
detection
UxTRB1
Read
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