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參數(shù)資料
| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 85/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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Application Information
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
85 of 118
April, 2002
outputs are tied to VDD, active low signals (otherwise the LED outputs
will indicate their respective opposite events.)
The LEDDEF pin determines the default settings for LED[3:0]. If LEDDEF
= 0, the default functions for LED[3:0] are Link 100, Activity, Full Duplex,
and Link 10, respectively. If LEDDEF = 1, the LED functions for LED[3:0]
are forced to LINK + ACTIVITY, Collision, Full Duplex and 10/100 Mbps
operation, respectively.
Table 4
defines the LED functions.
Table 5
defines the LED events.
The LED[3:0] outputs can also drive other digital inputs. Thus, LED[3:0]
can also be used as digital outputs whose function can be user defined
and controlled through the MI serial port.
4.14 5V Compatible I/O Operation
The input and output pins of the L84225 are tolerant of signal levels up
to a maximum of 5.5V (including overshoot etc.). This allows the
transceiver to be operated with 5V controllers that have TTL I/O
characteristics (0.8 to 2.0V Input levels) without the use of levelshifters
or other interfaces.
Controllers and other system components may be operated with 5V
supplies and all inter-chip signals may be connected directly to the
L84225. All required external logic levels must retain TTL compatibility
since the L84225 outputs are not guaranteed to achieve higher than 2.3V
with a load of 10ma. However, the inputs of the L84225 will tolerate TTL
or CMOS logic levels being driven into the device.
This should make replacement of the Physical Layer transceivers in
existing designs quite simple since any 5V devices do not need to be
changed.
4.15 Power Supply Decoupling
There are 18 VDDs and 19 GNDs on the L84225.
All VDDs on each individual side should be connected together
(grouped) and tied to a power plane, as close as possible to the L84225
supply pins. If the VDDs vary in potential by even a small amount, noise
and latchup can result. The L84225 VDD pins should be kept to within
50 mV of each other.
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