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參數資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數： | 52/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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52 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
The MI serial port is idle when at least 32 continuous 1's are detected
on MDIO and remains idle as long as continuous 1's are detected.
During idle, MDIO is in the high impedance state. When the MI serial port
is in the idle state, a 01 pattern on the MDIO pin initiates a serial shift
cycle. Data on MDIO is then shifted in on the next 14 rising edges of
MDC (MDIO is high impedance). If the register access mode is not
enabled, on the next 16 rising edges of MDC, data is either shifted in or
out on MDIO, depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles have been
completed, one complete register has been read/written, the serial shift
process is halted, data is latched into the device, and MDIO goes into
high impedance state. Another serial shift cycle cannot be initiated until
the idle condition (at least 32 continuous 1's) is detected.
2.25.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial port access
cycle with the multiple register access feature. The multiple register
access feature can be enabled by setting the multiple register access
enable bit in the Global Configuration Register for all channels.
When multiple register access is enabled, all registers can be accessed
on a single MI serial port access cycle by setting the register address to
11111 during the first 16 MDC clock cycles. There is no actual register
residing in register address location 11111.
When the register address is set to 11111, all eleven registers are
accessed for all four channels on the 704 rising edges of MDC (4 x 11
x 16) that occur after the first 16 MDC clock cycles of the MI serial port
access cycle. The registers are accessed in numerical order from 0 to
20 for each channel and from channel 0 to 3. After all 720 MDC clocks
have been completed, all the registers have been read/written, and the
serial shift process is halted, data is latched into the device, and MDIO
goes into high impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's) is detected.
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相關代理商/技術參數 |
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| L84225/B1 | 制造商:LSI Corporation 功能描述: |
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| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
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