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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊，4月2日 |
| 文件頁數(shù)： | 45/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
45 of 118
April, 2002
2.17 Full Duplex Mode
2.17.1 100 Mbps
Full Duplex mode allows transmission and reception to occur
simultaneously. When Full Duplex mode is enabled, collision is disabled,
and internal TXEN to CRS loopback is disabled.
The device can be either forced into Half or Full Duplex mode, or the
device can detect either Half or Full Duplex capability from a remote
device and automatically place itself in the correct mode.
Each channel can be forced into the Full or Half Duplex modes by either
setting the duplex bit in the MI serial port Control register or asserting
the DPLX pin for the corresponding channel with AutoNegotiation
disabled.
The device can automatically configure itself for Full or Half Duplex
modes by using the AutoNegotiation algorithm to advertise and detect
Full and Half Duplex capabilities to and from a remote terminal. For
detailed information, refer to
Section 2.14, “Link Integrity and
AutoNegotiation,” page 40
.
2.17.2 10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode.
2.17.3 Full Duplex Indication
Full Duplex detect activity can be monitored through the duplex detect bit
in the MI serial port Channel Status Output register.
Full Duplex detect activity also appears on the LED1 pin by default. The
LED outputs can be programmed to indicate four specific sets of events,
by appropriately setting the LED definition bits in the MI serial port Global
Configuration register.
Section 2.23, “LED Drivers,” page 48
, describes
the programmable LED definition bit settings. Note that Full Duplex
detection appears on the LED1 pin in each of the four sets of events.
The LED1 pin is asserted low when the device is configured for Full
Duplex operation.
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