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| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 34/118頁(yè) |
| 文件大小： | 890K |
| 代理商： | L84225 |
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April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
2.10.2 Transmitter
The FX transmitter converts data from the 4B5B encoder into binary
NRZI data and outputs the data onto the FXOP/FXON pins for each
channel. The output driver is a differential current source that will drive a
100-ohm load to ECL levels. The FXOP/FXON pins can directly drive an
external fiber optic transceiver. The FX transmitter meets all the
requirements defined in IEEE 802.3.
The FX transmit output current level is derived from an internal reference
voltage and the external resistor on REXT pin.
2.10.3 Receiver
The FX receiver (1) converts the differential ECL inputs on the
FXIP/FXIN pins for each channel to a digital bit stream, (2) validates the
data on FXIP/FXIN with the SD/ FXEN input pin for each channel, and
(3) enable/disables the Fiber Interface with the SD/FXEN pin for each
channel. The FX receiver meets all requirements defined in IEEE 802.3.
The input to the FXIP/FXIN pins can be directly driven from a fiber optic
transceiver and first goes to a comparator. The comparator compares the
input waveform against the internal ECL threshold levels to produce a
low jitter serial bit stream with internal logic levels. The data from the
comparator output is then passed to the clock and data recovery block
provided the signal detect input, SD/FXEN, is asserted. The signal detect
function is described in the next section.
2.10.4 Signal Detect
The FX receiver has a signal detect input pin, SD/FXEN, for each
channel which indicates whether the incoming data on FXIP/FXIN is valid
or not for that channel. The SD/FXEN pin can be driven directly from an
external fiber optic transceiver and meets all requirements defined in the
IEEE 802.3 specifications.
The SD/FXEN input goes directly to a comparator. The comparator
compares the input waveform against the internal ECL threshold level to
produce a digital signal with internal logic levels. The output of the signal
detect comparator then goes to the link integrity and squelch blocks. If
the signal detect input is asserted, the channel is placed in the Link Pass
state and the input data on FXIP/FXIN is determined to be valid. If the
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