參數(shù)資料
型號(hào): L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè),4月2日
文件頁數(shù): 11/118頁
文件大小: 890K
代理商: L84225
Pin Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
11 of 118
April, 2002
Table 2
LED Definitions as per the LEDDEF Pin
Name
Output State Description
LEDtied
to GND
LEDtied
to Vdd
LEDDEF
LED0
1
1. LED 0 becomes FEF when FX Interface is enabled.
0 = FEF detected
1 = No FEF detected
0 = 100 Mbps Link Detected
Off
On
LEDDEF = 1
(10/100)
1 = 10 Mbps Link Detected
On
Off
3-state = No Link
Off
Off
LED1
0 = Full Duplex Mode Detect with Link Pass
Off
On
(Fdx/Hdx)
1 = Half Duplex Mode Detect with Link Pass
On
Off
3-state = No Link
Off
Off
LED2
0 = Collision Detect
Off
On
(Col)
1 = No Collision
On
Off
LED3
0 = Link Detect
Off
On
(Link + Act)
Blink = Link Detect + Activity
Blink
Blink
1 = No Link Detect or Activity
On
Off
LED0
1
0 = 10 Mbps Link Detected
Off
On
LEDDEF = 0
(Link10)
1 = No 10 Mbps Link Detected
On
Off
LED1
0 = Full Duplex Mode Detect with Link Pass
Off
On
(Fdx/Hdx)
1 = Half Duplex Mode Detect with Link Pass
On
Off
3-state = No Link
Off
Off
LED2
Blink = Activity Occurred
(Stretch pulse to 100 ms)
Off
On
(Act)
1 = No Activity
On
Off
LED3
0 = Link100 Detected
Off
On
1 = No Link100
On
Off
(Link100)
Detected
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