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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 27/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
27 of 118
April, 2002
so that none of the individual scrambler sections on-chip will be
synchronous with the others to minimize EMI issues.
2.6.2 10 Mbps
A scrambler is not used in 10 Mbps mode.
2.6.3 Scrambler Bypass
The scrambler can be bypassed by setting the bypass
scrambler/descrambler bit in the MI serial port Channel Configuration
register. When this bit is set, the 5B data bypasses the scrambler and
goes directly from the 4B5B encoder to the twisted pair transmitter.
2.7 Descrambler
2.7.1 100 Mbps
The L84225 descrambler takes the scrambled data from the data
recovery block, descrambles it per the IEEE 802.3 specifications, aligns
the data on the correct 5B word boundaries, and sends it to the 4B5B
decoder.
The algorithm for synchronization of the descrambler is the same as the
algorithm outlined in the IEEE 802.3 specification. Once the descrambler
is synchronized, it will maintain synchronization as long as enough
descrambled idle pattern 1’s are detected within a given interval. To stay
in synchronization, the descrambler needs to detect at least 25
consecutive descrambled idle pattern 1’s in a 1 ms interval. If 25
consecutive descrambled idle pattern 1’s are not detected within the 1
ms interval, the descrambler goes out of synchronization and restarts the
synchronization process.
If the descrambler is in the unsynchronized state, the descrambler loss
of synchronization detect bit is set in the MI serial port Channel Status
Output register to indicate this condition. Once this bit is set, then it will
stay set until the descrambler achieves synchronization.
A descrambler is not used for FX operation.
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| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
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