參數(shù)資料
型號: L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊,4月2日
文件頁數(shù): 31/118頁
文件大小: 890K
代理商: L84225
Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
31 of 118
April, 2002
2.9.2 Receiver - 10 Mbps
The 10 Mbps mode receiver is much simpler than the 100 Mbps mode
receiver and is identical to the 100 Mbps receiver except:
The adaptive equalizer is disabled and bypassed.
The baseline wander correction circuit is disabled.
The 10 Mbps receiver is able to detect input signals from the twisted
pair cable that are within the template specified in IEEE 802.3 Clause
14 and shown in
Figure 5
.
The output of the squelch comparator is used for squelch, link pulse
detect, SOI detect, reverse polarity detect.
The data comparator is a zero crossing comparator whose output is
used for clock and data recovery.
2.9.3 Squelch - 100 Mbps
The squelch block determines whether the input contains valid data. The
100 Mbps TX squelch is one of the criteria used to determine link
integrity. The squelch comparators compare the TX inputs against fixed
positive and negative thresholds, called squelch levels.
The output from the squelch comparator goes to a digital squelch circuit,
which determines whether the receive input data on that channel is valid.
If the data is invalid, the receiver is in the squelched state. If the input
voltage exceeds the squelch levels at least four times with alternating
polarity within a 10 us interval, the data is considered to be valid by the
squelch circuit and the receiver now enters into the unsquelch state.
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