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參數(shù)資料
| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 22/118頁(yè) |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
2.2.9 MII Disable
The MII and FBI inputs and outputs can be disabled by setting the MII
disable bit in the MI serial port Control register. When the MII is disabled,
the inputs are ignored, the outputs are placed in high impedance state,
and the TP output is high impedance.
2.2.10 TXEN to CRS Loopback Disable
The internal TXEN to CRS loopback can be disabled by appropriately
setting the TXEN to CRS loopback disable bit in the MI serial port
Channel Configuration register. TXEN to CRS loopback is disabled in
RMII mode.
2.3 Encoder
2.3.1 4B5B Encoder - 100 Mbps
100BaseTX and 100BaseFX require that the data be 4B5B encoded.
4B5B coding converts the 4-bit data nibbles into 5-bit data words. The
mapping of the 4B nibbles to the 5B code words is specified in IEEE
802.3 and shown in
Table 3
. The 4B5B encoder on the L84225 takes 4B
nibbles from the controller interface, converts them into 5B words
according to
Table 3
, and sends the 5B words to the scrambler. The
4B5B encoder also substitutes the first eight bits of the preamble with the
SSD delimiters (/J/K/ symbols) and adds an ESD delimiter (/T/R/
symbols) to the end of each packet, as defined in IEEE 802.3 and shown
in
Figure 2
. The 4B5B encoder also fills the period between packets,
called the idle period, with a continuous stream of idle symbols, as
shown in
Figure 2
.
Table 3
4B/5B Symbol Mapping
Symbol Name
Description
5B Code
4B Code
0
Data 0
11110
0000
1
Data 1
01001
0001
2
Data 2
10100
0010
3
Data 3
10101
0011
4
Data 4
01010
0100
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