參數(shù)資料
型號: L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊,4月2日
文件頁數(shù): 39/118頁
文件大小: 890K
代理商: L84225
Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
39 of 118
April, 2002
and abnormally. When this premature end of packet condition is
detected, RXER remains asserted for the nibble associated with the first
/I/ symbol detected and then RXER and CRS and RXDV are all
deasserted. Premature end of packet condition is also indicated by
setting the ESD error bit in the MI serial port Channel Status Output
register.
2.13.2 10 Mbps
The end of packet for 10 Mbps mode is indicated with the SOI (Start of
Idle) pulse. The SOI pulse is a positive double wide pulse containing a
Manchester code violation inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter and inserted
at the end of the data packet after TXEN is deasserted. The transmitted
SOI output pulse at the TP output is shaped by the transmit waveshaper
to meet the pulse template requirements specified in IEEE 802.3 Clause
14 and shown in
Figure 6
.
The receive SOI pulse is detected by the TP receiver by sensing missing
data transitions. Once the SOI pulse is detected, data reception is ended
and CRS and RXDV are deasserted.
Figure 6
SOI Output Voltage Template - 10 Mbps
0 BT
4.5 BT
6.0 BT
+50 mV
50 mV
45.0 BT
4.5 BT
2.5 BT
3.1 V
0.25 BT2.25 BT
585 mV
3.1 V
0.5 V/ns
585 mV sin (2
π
(t/1 BT))
0
t
0.25 BT and
2.25
t
2.5 BT
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