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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 36/118頁 |
| 文件大小： | 890K |
| 代理商： | L84225 |
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36 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
2.11 Collision
2.11.1 100 Mbps
Collision occurs whenever transmit and receive occur simultaneously
while the device is in Half Duplex. Collision is sensed whenever there is
simultaneous transmission (packet transmission on TPOP/N) and
reception (non-idle symbols detected on receive input). When collision is
detected:
The COL output is asserted.
TP data continues to be transmitted on twisted pair outputs.
TP data continues to be received on twisted pair inputs.
Internal CRS loopback is disabled.
Once collision starts, CRS is asserted and stays asserted until the
receive and transmit packets that caused the collision are terminated.
The collision function is disabled if the device is in the Full Duplex mode,
is in the Link Fail state, or if the device is in the diagnostic loopback
mode.
2.11.2 10 Mbps
Collision in 10 Mbps mode is identical to the 100 Mbps mode, except:
Reception is determined by the 10 Mbps squelch criteria.
RXD[3:0] outputs are forced to all 0's.
Collision is asserted when the SQE test is performed.
Collision is asserted when the jabber condition has been detected.
2.11.3 Collision Test
The controller interface collision signal, COL, can be tested by setting the
collision test register bit in the MI serial port Control register. When this
bit is set, TXEN is looped back onto COL and the TP outputs are
disabled.
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