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參數(shù)資料
| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 20/118頁(yè) |
| 文件大小： | 890K |
| 代理商： | L84225 |
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April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
The CLKIN clock frequency must be 50 MHz instead of 25 MHz.
All timing for both transmit and receive is referenced to a single clock
on CLKIN instead of TXCLK for transmit and RXCLK for receive.
An elastic buffer is present in the receive data path to account for
any difference between the CLKIN and receive data frequencies. The
elastic buffer is 32 bits in length. Input data from the receiver fills the
buffer to a predetermined threshold level before data is passed to the
RMII outputs. This threshold level can be configured to either 4 bits
or 16 bits by appropriately setting the RMII threshold select bit in the
MI serial port Global Configuration register.
The MII RXDV and CRS inputs are combined into one signal that is
outputted on the CRS pin. CRS is asserted active high when
incoming packet data is detected on the receive inputs. It stays
asserted high until packet data is no longer detected, and it toggles
at a 25 MHz rate (low for first di-bit of MII nibble, high for second,
etc.) from the end of the packet data detection until end of valid data
transfer from the elastic buffer. During this toggling interval, valid data
is still being output on RXD[1:0]. CRS is finally deasserted when all
data has been output from the internal elastic buffer on RXD[1:0].
RXD[1:0]=00 from start of CRS until valid data is ready to be output.
TXEN to CRS loopback is disabled.
Any packet that contains an error will assert RXER and substitute
RXD[1:0]=10 for all the data bits from the error detect point until the
end of packet.
2.2.5 RMII - 10 Mbps
10 Mbps RMII operation is identical to 100 Mbps RMII operation, except:
The CLKIN frequency remains at 50 Mhz (same as 100 Mbps
operation).
Each data di-bit must be input on TXD[1:0] for ten consecutive
CLKIN cycles.
Each data di-bit will be output on RXD[1:0] for ten consecutive
CLKIN cycles.
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