參數(shù)資料
型號(hào)： L84225
英文描述： L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述： L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日
文件頁數(shù)： 57/118頁
文件大?。?/td> 890K
代理商： L84225
Register Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
57 of 118
April, 2002
3 Register Description
Table 8
MI Serial Port Structure
<Idle>
IDLE
<Start>
ST[1:0]
<Read>
READ
<Write>
WRITE
<PHY Addr.>
PHYAD[4:0]
<Reg. Addr.>
REGAD[4:0]
<Turnaround>
TA[1:0]
<Data>
D[15:0]
MI Registers - Address and Default Value
REGAD
Name
Default (Hex Code)
00000
00001
00010
00011
00100
00101
10000
10001
10010
10011
10100
Control Register
Status Register
PHY ID 1 Register
PHY ID 2 Register
Auto Negotiation Advertisement Register
Auto Negotiation Remote Capability Register
Reserved
Reserved
Channel Status Output Register
Reserved
Reserved
3000
7809
0016
F840
01E1
0000
0008
0002
0340/0240/ 0140/0040
007F
0000
Symbol
Name
Definition
R/W
IDLE
Idle Pattern
These bits are an idle pattern. Device will not initiate an MI
cycle until it detects at least 32 1's.
When ST[1:0]=01, a MI serial port access cycle starts.
1 = Read Cycle
1 = Write Cycle
When PHYAD[4:2] bits match the PHYAD[4:2] pins, the MI
serial port is selected for operation. PHYAD[1:0] is used for
channel selection:
PHYAD [1:0]=11 For Channel 3
PHYAD [1:0]=10 For Channel 2
PHYAD [1:0]=01 For Channel 1
PHYAD [1:0]=00 For Channel 0
If REGAD[4:0]=00000-11100, these bits determine the
specific register from which D[15:0] is read/written. If mul-
tiple register access is enabled and REGAD[4:0]=11111,
all registers are read/written in a single cycle.
W
ST[1:0]
READ
WRITE
PHYAD[4:0]
Start Bits
Read Select
Write Select
PhysicalDevice
Address
W
W
W
W
REGAD4[4:0]
Register
Address
W
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參數(shù)描述
L84225/B1 制造商:LSI Corporation 功能描述:
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