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參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 84/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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84 of 118
April, 2002
L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
as shown in
Table 24
. Note that these pins
should not float
, but must be
connected either High or Low for proper operation.
In order to obtain the “Default Mode of Operation”, i.e.: Auto-negotiation
enabled, 100MBs, and Half Duplex; the ANEG, SPEED_[3:0], and
DPLX_[3:0] pins should be set to 1,1,0 respectively.
4.11 Long Cable
IEEE 802.3 specifies that 10BaseT and 100BaseTX operate over twisted
pair cable lengths from 0 to 100 meters. The squelch levels can be
reduced by 4.5 dB if the receive level adjust bit is appropriately set in the
MI serial port Channel Configuration register, which will allow the L84225
to operate with up to 150 meters of twisted pair cable. The equalizer is
already designed to accommodate between 0 to 150 meters of cable.
4.12 Clock
The L84225 requires a 25 MHz reference frequency for internal signal
generation in MII mode, and 50 MHz in RMII mode. The appropriate
reference frequency must be applied to the CLKIN pin.
4.13 LED Drivers
The LED[3:0] outputs can all drive LED’s tied to VDD as shown in
Figure 11
and
Figure 12
. In addition, the LED[3:0] outputs can drive
LEDs tied to GND as well. The LED definitions assume that the LED
Table 24
Hardware Configuration
Configuration
State
Auto-Negotiate
Speed
Duplex
Normal
(POC/RESET)
Enabled
Advertise 10/100
Advertise Full/Half
Config Pins
ANEG=1
SPEED_[3:0]=1
DPLX_[3:0]=0
Complement State
Disabled
10MBs
Full
Config Pins
ANEG=0
SPEED_[3:0]=0
DPLX_[3:0]=1
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