參數(shù)資料
型號： CY7C67200
廠商： Cypress Semiconductor Corp.
英文描述： EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器)
中文描述： 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器）
文件頁數(shù)： 75/82頁
文件大?。?/td> 1719K
代理商： CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 75 of 82
15.6
HSS BYTE Mode Transmit
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera-
tions and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
15.7
HSS Block Mode Transmit
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, t
GAP
= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
Transmit Gap register 90xC074].
The default t
GAP
is 2 BT.
BT = bit time = 1/baud rate.
15.8
HSS BYTE and BLOCK Mode Receive
Receive data arrives asynchronously relative to the internal clock.
Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or
higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
CPU may start another BYTE
transmit right after TxRdy
goes high
start of last data bit to TxRdy high:
0 min, 4 T max.
(T is qt_clk period)
TxRdy low to start bit delay:
0 min, BT max when starting from IDEL.
For back to back transmit, new START Bit
begins immediately following previous STOP bit.
(BT = bit period)
BT
BT
start bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
qt_clk
CPU_A[2:0]
CPUHSS_cs
CPU_wr
TxRdy flag
HSS_TxD
Byte transmit
triggered by a
CPU write to the
HSS_TxData register
stop bit
start bit
programmable
1 or 2 stop bits.
1 stop bit shown.
HSS_TxD
t
GAP
BT
BT +/- 5%
start bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
stop bit
start bit
HSS_RxD
BT +/- 5%
10 BT +/- 5%
received byte added to
receive FIFO during the final data bit time
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C672001-48BAXI 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C672001-48BAXIT 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CY7C67200-48BAXI 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C67200-48BAXIT 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C67300-100AI 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC
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