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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器） |
| 文件頁數(shù)： | 3/82頁 |
| 文件大?。?/td> | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 3 of 82
5.1
EZ-OTG has two built-in Host/Peripheral SIE’s that each have
a single USB transceiver, meeting the USB 2.0 specification
requirements for full- and low-speed (high-speed is not sup-
ported). In Host mode, EZ-OTG supports two downstream
ports; each supports control, interrupt, bulk, and isochronous
transfers. In Peripheral mode, EZ-OTG supports one periph-
eral port with eight endpoints for each of the two SIE’s. End-
point 0 is dedicated as the control endpoint and only supports
control transfers. Endpoints 1 though 7 support Interrupt, bulk
(up to 64 bytes per packet), or isochronous transfers (up to
1023 bytes per packet size). EZ-OTG also supports a combi-
nation of Host and Peripheral ports simultaneously as shown
in
Table 5-2
.
USB Interface
5.1.1
USB 2.0 compatible for full- and low-speed
Up to two downstream USB host ports
Up to two upstream USB peripheral ports
Configurable endpoint buffers (pointer and length), must
reside in internal RAM
Up to eight available peripheral endpoints (1 control
endpoint)
Supports Control, Interrupt, Bulk, and Isochronous transfers
Internal DMA channels for each endpoint
Internal pull up and pull down resistors
Internal Series termination resistors on USB data lines
USB Features
5.1.2
USB Pins
5.2
EZ-OTG has one USB port that is compatible with the USB
On-The-Go supplement to the USB 2.0 specification. The USB
OTG port has various hardware features to support Session
Request Protocol (SRP) and Host Negotiation Protocol (HNP).
OTG is only supported on USB PORT 1A.
OTG Interface
5.2.1
Internal Charge Pump to supply and control VBUS
VBUS Valid Status (above 4.4V)
VBUS Status for 2.4V< VBUS <0.8V
ID Pin Status
Switchable 2 Kohm
internal discharge resistor on VBUS
Switchable 500 ohm internal pull up resistor on VBUS
Individually switchable internal pull up and pull down
resistors on the USB data lines
OTG Features
5.2.2
OTG Pins
5.3
EZ-OTG has up to 25 GPIO signals available. Several other
optional interfaces use GPIO pins as well and may reduce the
overall number of available GPIO’s.
General Purpose IO Interface
5.3.1
All Inputs are sampled asynchronously with state changes oc-
curring at a rate of up to two 48 MHZ clock cycles. GPIO pins
are latched directly into registers, a single flip-flop.
GPIO Description
5.3.2
Unused USB pins must be tri-stated with the D+ line pulled
high through the internal pull up resistor and the D- line pulled
low through the internal pull down resistor.
Unused GPIO pins must be configured as outputs and driven
low.
Unused Pin Descriptions
5.4
EZ-OTG has a built-in UART interface. The UART interface
supports data rates from 900 to 115.2K baud. It can be used
as a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
UART Interface
Table 5-2. USB Port Configuration Options
Port Configurations
OTG
OTG + 1 Host
OTG + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
2 Hosts
1 Host
1 Host
2 Peripherals
1 Peripheral
1 Peripheral
Port 1A
OTG
OTG
OTG
Host
Peripheral
Host
Host
–
Peripheral
Peripheral
–
Port 2A
–
Host
Peripheral
Peripheral
Host
Host
–
Host
Peripheral
–
Peripheral
Table 5-3. USB Interface Pins
Pin Name
DM1A
DP1A
DM2A
DP2A
Pin Number
F2
E3
C2
D3
Table 5-4. OTG Interface Pins
Pin Name
DM1A
DP1A
OTGVBUS
OTGID
CSwitchA
CSwitchB
Pin Number
F2
E3
C1
F4
D1
D2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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