參數(shù)資料
型號: CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁數(shù): 40/82頁
文件大小: 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 40 of 82
The SOF/EOP count must be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements at a
12-MHz rate. Therefore in the case of an expected 1-ms SOF/EOP interval, the SOF/EOP count must be set slightly greater then
0x2EE0.
Count
(Bits [13:0])
The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and
for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly.
Reserved
All reserved bits must be written as ‘0’.
8.6
There is one register dedicated for OTG operation. This register is covered in this section and summarized in
Figure 8-39
.
OTG Control Registers
8.6.1
OTG Control Register [0xC098] [R/W]
Figure 8-40. OTG Control Register
Register Description
The OTG Control register allows control and monitoring over the OTG port on Port1A.
VBUS Pull-up Enable
(Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500 ohm pull up resistor onto OTG VBus.
1:
500 ohm pull up resistor enabled
0:
500 ohm pull up resistor disabled
Receive Disable
(Bit 12)
The Receive Disable bit enables or powers down (disables) the OTG receiver section.
1:
OTG receiver powered down and disabled
0:
OTG receiver enabled
Figure 8-39. OTG Registers
Register Name
OTG Control Register
Address
C098H
R/W
R/W
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
VBUS
Pull-up
Enable
Receive
Disable
Charge Pump
Enable
VBUS
Discharge
Enable
D+
Pull-up
Enable
D–
Pull-up
Enable
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
D+
Pull-down
Enable
D–
Pull-down
Enable
Reserved
OTG Data
Status
ID
Status
VBUS Valid
Flag
Read/Write
R/W
R/W
-
-
-
R
R
R
Default
0
0
0
0
0
X
X
X
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