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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機/外設控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設備控制器） |
| 文件頁數(shù)： | 26/82頁 |
| 文件大?。?/td> | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 26 of 82
ID Interrupt Enable
(Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both rising and falling
edge of OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1:
Enable ID interrupt
0:
Disable ID interrupt
SOF/EOP Interrupt Enable
(Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt.
1:
Enable SOF/EOP timer interrupt
0:
Disable SOF/EOP timer interrupt
Port A Wake Interrupt Enable
(Bit 6)
The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A.
1:
Enable remote wakeup interrupt for Port A
0:
Disable remote wakeup interrupt for Port A
Port A Connect Change Interrupt Enable
(Bit 4)
The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt
triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1:
Enable Connect Change interrupt
0:
Disable Connect Change interrupt
Done Interrupt Enable
(Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either
the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt
is used for both Port A and Port B.
1:
Enable USB Transfer Done interrupt
0:
Disable USB Transfer Done interrupt
Reserved
All reserved bits must be written as ‘0’.
8.4.9
Host 1 Status Register 0xC090
Host 2 Status Register 0xC0B0
Host n Status Register [R/W]
Figure 8-24. Host n Status Register
Register Description
The Host n Status register provides status information for host operation. Pending interrupts can be cleared by writing a ‘1’ to the
corresponding bit. This register can be accessed by the HPI interface.
Bit #
15
14
13
12
11
10
9
8
Field
VBUS
Interrupt Flag
ID Interrupt
Flag
Reserved
SOF/EOP
Interrupt Flag
Reserved
Read/Write
R/W
R/W
-
-
-
-
R/W
-
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
Port A
Wake Interrupt
Flag
Reserved
Port A Connect
Change
Interrupt Flag
Reserved
Port A
SE0
Status
Reserved
Done
Interrupt Flag
Read/Write
-
R/W
-
R/W
-
R/W
-
R/W
Default
X
X
X
X
X
X
X
X
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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