參數(shù)資料
型號: CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器)
文件頁數(shù): 41/82頁
文件大小: 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 41 of 82
Charge Pump Enable
(Bit 11)
The Charge Pump Enable bit enables or disables the OTG
VBus charge pump.
1:
OTG VBus charge pump enabled
0:
OTG VBus charge pump disabled
VBUS Discharge Enable
(Bit 10)
The VBUS Discharge Enable bit enables or disables a 2K ohm
discharge pull down resistor onto OTG VBus.
1:
2K ohm pull down resistor enabled
0:
2K ohm pull down resistor disabled
D+ Pull-up Enable
(Bit 9)
The D+ Pull-up Enable bit enables or disables a pull up resistor
on the OTG D+ data line.
1:
OTG D+ dataline pull up resistor enabled
0:
OTG D+ dataline pull up resistor disabled
D– Pull-up Enable
(Bit 8)
The D– Pull-up Enable bit enables or disables a pull up resistor
on the OTG D– data line.
1:
OTG D– dataline pull up resistor enabled
0:
OTG D– dataline pull up resistor disabled
D+ Pull-down Enable
(Bit 7)
The D+ Pull-down Enable bit enables or disables a pull down
resistor on the OTG D+ data line.
1:
OTG D+ dataline pull down resistor enabled
0:
OTG D+ dataline pull down resistor disabled
D– Pull-down Enable
(Bit 6)
The D– Pull-down Enable bit enables or disables a pull down
resistor on the OTG D- data line.
1:
OTG D– dataline pull down resistor enabled
0:
OTG D– dataline pull down resistor disabled
OTG Data Status
(Bit 2)
The OTG Data Status bit is a read only bit and indicates the
TTL logic state of the OTG VBus pin.
1:
OTG VBus is greater than 2.4V
0:
OTG VBus is less than 0.8V
ID Status
(Bit 1)
The ID Status bit is a read only bit that indicates the state of
the OTG ID pin on Port A.
1:
OTG ID Pin is not connected directly to ground (>10K ohm)
0:
OTG ID Pin is connected directly ground (< 10 ohm)
VBUS Valid Flag
(Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is
greater than 4.4V. After turning on VBUS, firmware should wait
at least 10 μs before this reading this bit.
1:
OTG VBus is greater then 4.4V
0:
OTG VBus is less then 4.4V
Reserved
All reserved bits must be written as ‘0’.
8.7
There are seven registers dedicated for GPIO operations.
These seven registers are covered in this section and summa-
rized in
Figure 8-41
.
GPIO Registers
Figure 8-41. GPIO Registers
Register Name
GPIO Control Register
GPIO0 Output Data Register
GPIO0 Input Data Register
GPIO0 Direction Register
GPIO1 Output Data Register
GPIO1 Input Data Register
GPIO1 Direction Register
Address
0xC006
0xC01E
0xC020
0xC022
0xC024
0xC026
0xC028
R/W
R/W
R/W
R
R/W
R/W
R
R/W
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