參數(shù)資料
型號(hào): CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁(yè)數(shù): 10/82頁(yè)
文件大?。?/td> 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 10 of 82
8.0
Registers
Some registers have different functions for a read vs. a write
access or USB host vs. USB device mode. Therefore,
registers of this type will have multiple definitions for the same
address.
The default register values listed in this data sheet may get
altered to some other value during BIOS initialization. Refer to
the BIOS documentation for Register initialization information.
8.1
There are eight registers dedicated to general processor
control. Each of these registers is covered in this section and
is summarized in
Figure 8-1
.
Processor Control Registers
8.1.1
CPU Flags Register [0xC000] [R]
Figure 8-2. CPU Flags Register
Register Description
The CPU Flags register is a read only register that gives
processor flags status.
Global Interrupt Enable
(Bit 4)
The Global Interrupt Enable bit indicates if the Global Inter-
rupts are enabled.
1:
Enabled
0:
Disabled
Negative Flag
(Bit 3)
The Negative Flag bit indicates if an arithmetic operation
results in a negative answer.
1:
MS result bit is ‘1’
0:
MS result bit is not ‘1’
Overflow Flag
(Bit 2)
The Overflow Flag bit indicates if an overflow condition has
occurred. An overflow condition can occur if an arithmetic
result was either larger than the destination operand size (for
addition) or smaller than the destination operand should allow
for subtraction.
1:
Overflow occurred
0:
Overflow did not occur
Carry Flag
(Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted
in a carry for addition, or borrow for subtraction.
1:
Carry/Borrow occurred
0:
Carry/Borrow did not occur
Zero Flag
(Bit 0)
The Zero Flag bit indicates if an instruction execution resulted
in a ‘0’.
1:
Zero occurred
0:
Zero did not occur
Figure 8-1. Processor Control Registers
Register Name
CPU Flags Register
Register Bank Register
Hardware Revision Register
CPU Speed Register
Power Control Register
Interrupt Enable Register
Breakpoint Register
USB Diagnostic Register
Address
0xC000
0xC002
0xC004
0xC008
0xC00A
0xC00E
0xC014
0xC03C
R/W
R
R/W
R
R/W
R/W
R/W
R/W
W
Bit #
15
14
13
12
11
10
9
8
Field
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Global
Interrupt
Enable
Negative
Flag
Overflow
Flag
Carry
Flag
Zero
Flag
Read/Write
-
-
-
R
R
R
R
R
Default
0
0
0
X
X
X
X
X
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