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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設(shè)備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機/外設(shè)控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設(shè)備控制器） |
| 文件頁數(shù)： | 58/82頁 |
| 文件大小： | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 58 of 82
8.10.2
SPI Control Register [0xC0CA] [R/W]
Figure 8-66. SPI Control Register
Register Description
The SPI Control register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
SCK Strobe
(Bit 15)
The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration register), but not
phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self clearing.
1:
SCK Strobe Enable
0:
No Function
FIFO Init
(Bit 14)
The FIFO Init bit initializes the FIFO and clear the FIFO Error Status bit. This bit is self clearing.
1:
FIFO Init Enable
0:
No Function
Byte Mode
(Bit 13)
The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.
1:
Set PIO (byte mode) operation
0:
Set DMA (block mode) operation
Full Duplex
(Bit 12)
The Full Duplex bit selects between full duplex and half duplex operation.
1:
Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration register is set to ‘1’
0:
Enable half duplex operation
SS Manual
(Bit 11)
The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control register is all zeros and is configured
as master interface. This field only applies to master mode.
1:
Activate SS, master drives SS line asserted LOW
0:
Deactivate SS, master drives SS line deasserted HIGH
Read Enable
(Bit 10)
The Read Enable bit initiates a read phase for a master mode transfer or set the slave to receive (in slave mode).
1:
Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until
the read transfer begins.
0:
Initiates the write phase for slave operation
Transmit Ready
(Bit 9)
The Transmit Ready bit is a read only bit that indicates if the transmit port is ready to empty and ready to be written.
1:
Ready for data to be written to the port. The transmit FIFO is not full.
0:
Not ready for data to be written to the port
Bit #
15
14
13
12
11
10
9
8
Field
SCK
Strobe
FIFO
Init
Byte
Mode
Full Duplex
SS
Manual
Read
Enable
Transmit
Ready
Receive
Data Ready
Read/Write
W
W
R/W
R/W
R/w
R/W
R
R
Default
0
0
0
0
0
0
0
1
Bit #
7
6
5
4
3
2
1
0
Field
Transmit
Empty
Receive
Full
Transmit Bit Length
Receive Bit Length
Read/Write
R
R
R/W
R/W
R/W
R/W
R/w
R/W
Default
1
0
0
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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