參數(shù)資料
型號(hào): CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁(yè)數(shù): 4/82頁(yè)
文件大小: 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 4 of 82
5.4.1
Supports baud rates of 900 to 115.2K
8-N-1
UART Features
5.4.2
UART Pins
5.5
EZ-OTG provides a master only I2C interface for external se-
rial EEPROM’s. The serial EEPROM can be used to store ap-
plication specific code and data. This I2C interface is only to
be used for loading code out of EEPROM, it is not a general
I2C interface. The I2C EEPROM interface is a BIOS imple-
mentation and is exposed through GPIO pins. Refer to the
BIOS documentation for additional details on this interface.
I
2
C EEPROM Interface
5.5.1
Supports EEPROM’s up to 64 KB (512K bit)
Auto-detection of EEPROM size
I
2
C EEPROM Features
5.5.2
I
2
C EEPROM Pins
5.6
EZ-OTG provides an SPI interface for added connectivity. EZ-
OTG may be configured as either an SPI master or SPI slave.
The SPI interface can be exposed through GPIO pins or the
External Memory port.
Serial Peripheral Interface
5.6.1
Master or slave mode operation
DMA block transfer and PIO byte transfer modes
Full duplex or half duplex data communication
8-byte receive FIFO and 8-byte transmit FIFO
Selectable master SPI clock rates from 250 kHz to 12 MHz
Selectable master SPI clock phase and polarity
Slave SPI signaling synchronization and filtering
Slave SPI clock rates up to 2 MHz
Maskable interrupts for block and byte transfer modes
SPI Features
Individual bit transfer for non-byte aligned serial communi-
cation in PIO mode
Programmable delay timing for the active/in-active master
SPI clock
Auto or manual control for master mode slave select signal
Complete access to internal memory
5.6.2
The SPI port has a few different pin location options as shown
in
Table 5-7
. The pin location is selectable via the GPIO Con-
trol register [0xC006].
SPI Pins
5.7
EZ-OTG provides an HSS interface. The HSS interface is a
programmable serial connection with baud rate from 9600
baud to 2M baud. The HSS interface supports both byte and
block mode operations as well as hardware and software
handshaking. Complete control of EZ-OTG can be accom-
plished through this interface via an extensible API and com-
munication protocol. The HSS interface can be exposed
through GPIO pins or the External Memory port.
High-Speed Serial Interface
5.7.1
8-bit, no parity code
Programmable baud rate from 9600 baud to 2M baud
Selectable 1- or 2-stop bit on transmit
Programmable inter-character gap timing for Block
Transmit
8-byte receive FIFO
Glitch filter on receive
Block mode transfer directly to/from EZ-OTG internal
memory (DMA transfer)
Selectable CTS/RTS hardware signal handshake protocol
Selectable XON/XOFF software handshake protocol
Programmable Receive interrupt, Block Transfer Done
interrupts
Complete access to internal memory
HSS Features
5.7.2
HSS Pins
Table 5-5. UART Interface Pins
Pin Name
TX
RX
Pin Number
B5
B4
Table 5-6. I
2
C EEPROM Interface Pins
Pin Name
Pin Number
SMALL EEPROM
SCK
SDA
H3
F3
LARGE EEPROM
SCK
SDA
F3
H3
Table 5-7. SPI Interface Pins
Pin Name
nSSI
SCK
MOSI
MISO
Pin Number
F6 or C6
D5
D4
C5
Table 5-8. HSS Interface Pins
Pin Name
CTS
RTS
RX
TX
Pin Number
F6
E4
E5
E6
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