參數(shù)資料
型號(hào): CY7C67200
廠商: Cypress Semiconductor Corp.
英文描述: EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機(jī)/外圍設(shè)備控制器)
中文描述: 的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外設(shè)控制器(的EZ - OTG公司可編程的USB On - The - Go的主機(jī)/外圍設(shè)備控制器)
文件頁(yè)數(shù): 23/82頁(yè)
文件大?。?/td> 1719K
代理商: CY7C67200
CY7C67200
Document #: 38-08014 Rev. *F
Page 23 of 82
Sequence Status
(Bit 3)
The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring
and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to ‘0’ when
an error is detected in the transaction and the Error bit will be set.
1:
DATA1
0:
DATA0
Timeout Flag
(Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes too long to respond with a handshake.
1:
Timeout occurred
0:
Timeout did not occur
Error Flag
(Bit 1)
The Error Flag bit indicates a transaction failed for any reason other than the following: Timeout, receiving a NAK, or receiving a
STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in an
Error flag along with receiving incorrect packet types.
1:
Error detected
0:
No error detected
ACK Flag
(Bit 0)
The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochronous transfers, this bit
represents a transaction ending by receiving or sending an ACK packet. For Isochronous transfers, this bit represents a
successful transaction that will not be represented by an ACK packet.
1:
For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completed
successfully.
0:
For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction did not completed
successfully.
8.4.5
Host 1 PID Register 0xC086
Host 2 PID Register 0xC0A6
Host n PID Register [W]
Figure 8-20. Host n PID Register
Register Description
The Host n PID register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in the
next transaction.
PID Select
(Bits [7:4])
The PID Select field defined as in
Table 8-7
. ACK and NAK tokens are automatically sent based on settings in the Host n Control
register and do not need to be written in this register.
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
PID Select
Endpoint Select
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
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