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參數(shù)資料
| 型號： | CY7C67200 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-OTG Programmable USB On-The-Go Host/Peripheral Controller(EZ-OTG可編程USB On-The-Go主機/外圍設備控制器) |
| 中文描述： | 的EZ - OTG公司可編程的USB On - The - Go的主機/外設控制器（的EZ - OTG公司可編程的USB On - The - Go的主機/外圍設備控制器） |
| 文件頁數(shù)： | 35/82頁 |
| 文件大小： | 1719K |
| 代理商： | CY7C67200 |
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CY7C67200
Document #: 38-08014 Rev. *F
Page 35 of 82
8.5.6
Device 1 Interrupt Enable Register 0xC08C
Device 2 Interrupt Enable Register 0xC0AC
Device n Interrupt Enable Register [R/W]
Figure 8-34. Device n Interrupt Enable Register
Register Description
The Device n Interrupt Enable register provides control over
device related interrupts including eight different endpoint
interrupts.
VBUS Interrupt Enable
(Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both
rising and falling edge of VBUS at the 4.4V status (only
supported in Port 1A). This bit is only available for Device 1
and is a reserved bit in Device 2.
1:
Enable VBUS interrupt
0:
Disable VBUS interrupt
ID Interrupt Enable
(Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both rising
and falling edge of OTG ID pin (only supported in Port 1A).
This bit is only available for Device 1 and is a reserved bit in
Device 2.
1:
Enable ID interrupt
0:
Disable ID interrupt
SOF/EOP Time-out Interrupt Enable
(Bit 11)
The SOF/EOP Time-out Interrupt Enable bit enables or
disables the SOF/EOP Time-out Interrupt. When enabled this
interrupt triggers when the USB host fails to send a SOF or
EOP packet within the time period specified in the Device n
SOF/EOP Count register. In addition, the Device n Frame
register counts the number of times the SOF/EOP Timeout
Interrupt triggers between receiving SOF/EOPs.
1:
SOF/EOP time-out occurred
0:
SOF/EOP time-out did not occur
SOF/EOP Interrupt Enable
(Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP received interrupt.
1:
Enable SOF/EOP Received interrupt
0:
Disable SOF/EOP Received interrupt
Reset Interrupt Enable
(Bit 8)
The Reset Interrupt Enable bit enables or disables the USB
Reset Detected interrupt
1:
Enable USB Reset Detected interrupt
0:
Disable USB Reset Detected interrupt
EP7 Interrupt Enable
(Bit 7)
The EP7 Interrupt Enable bit enables or disables endpoint
seven (EP7) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN
Exception Error, or OUT Exception Error. In addition, the NAK
Interrupt Enable bit in the Device n Endpoint Control register
can also be set so that NAK responses triggers this interrupt.
1:
Enable EP7 Transaction Done interrupt
0:
Disable EP7 Transaction Done interrupt
EP6 Interrupt Enable
(Bit 6)
The EP6 Interrupt Enable bit enables or disables endpoint
seven (EP6) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN
Exception Error, or OUT Exception Error. In addition, the NAK
Interrupt Enable bit in the Device n Endpoint Control register
can also be set so that NAK responses triggers this interrupt.
1:
Enable EP6 Transaction Done interrupt
0:
Disable EP6 Transaction Done interrupt
Bit #
15
14
13
12
11
10
9
8
Field
VBUS
Interrupt
Enable
ID Interrupt
Enable
Reserved
SOF/EOP
Time-out
Interrupt Enable
Reserved
SOF/EOP
Interrupt
Enable
Reset
Interrupt
Enable
Read/Write
R/W
R/W
-
-
R/W
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
EP7 Interrupt
Enable
EP6 Interrupt
Enable
EP5 Interrupt
Enable
EP4 Interrupt
Enable
EP3 Interrupt
Enable
EP2 Interrupt
Enable
EP1 Interrupt
Enable
EP0 Interrupt
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C672001-48BAXI | 功能描述:8位微控制器 -MCU CY7C672001-48BAXI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C672001-48BAXIT | 功能描述:8位微控制器 -MCU CY7C672001-48BAXIT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C67200-48BAXI | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67200-48BAXIT | 功能描述:USB 接口集成電路 LO PWR OTG IND RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C67300-100AI | 制造商:Cypress Semiconductor 功能描述:INTERFACE MISC |
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